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git01.mediatek.com / filogic / uboot / 532c1581e5267d3c51129843e4fd986c7d03245a / . / board / m5282evb / u-boot.lds
blob: dd2666b764f16c0a38e035c4cdcb3a372ca112a0 [file] [log] [blame]
wdenkabf7a7c2003-12-08 01:34:36 +0000[diff] [blame]1/*
2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24OUTPUT_ARCH(m68k)
wdenkabf7a7c2003-12-08 01:34:36 +0000[diff] [blame]25/* Do we need any of these for elf?
26 __DYNAMIC = 0; */
27SECTIONS
28{
29 /* Read-only sections, merged into text segment: */
30 . = + SIZEOF_HEADERS;
31 .interp : { *(.interp) }
32 .hash : { *(.hash) }
33 .dynsym : { *(.dynsym) }
34 .dynstr : { *(.dynstr) }
35 .rel.text : { *(.rel.text) }
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]36 .rela.text : { *(.rela.text) }
wdenkabf7a7c2003-12-08 01:34:36 +0000[diff] [blame]37 .rel.data : { *(.rel.data) }
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]38 .rela.data : { *(.rela.data) }
39 .rel.rodata : { *(.rel.rodata) }
40 .rela.rodata : { *(.rela.rodata) }
wdenkabf7a7c2003-12-08 01:34:36 +0000[diff] [blame]41 .rel.got : { *(.rel.got) }
42 .rela.got : { *(.rela.got) }
43 .rel.ctors : { *(.rel.ctors) }
44 .rela.ctors : { *(.rela.ctors) }
45 .rel.dtors : { *(.rel.dtors) }
46 .rela.dtors : { *(.rela.dtors) }
47 .rel.bss : { *(.rel.bss) }
48 .rela.bss : { *(.rela.bss) }
49 .rel.plt : { *(.rel.plt) }
50 .rela.plt : { *(.rela.plt) }
51 .init : { *(.init) }
52 .plt : { *(.plt) }
53 .text :
54 {
55 /* WARNING - the following is hand-optimized to fit within */
56 /* the sector layout of our flash chips! XXX FIXME XXX */
57
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]58 cpu/mcf52x2/start.o (.text)
wdenkabf7a7c2003-12-08 01:34:36 +0000[diff] [blame]59 common/dlmalloc.o (.text)
60 lib_generic/string.o (.text)
61 lib_generic/vsprintf.o (.text)
62 lib_generic/crc32.o (.text)
63 lib_generic/zlib.o (.text)
64
65/* . = env_offset; */
66 common/environment.o(.text)
67
68 *(.text)
69 *(.fixup)
70 *(.got1)
71 }
72 _etext = .;
73 PROVIDE (etext = .);
74 .rodata :
75 {
76 *(.rodata)
77 *(.rodata1)
78 }
79 .fini : { *(.fini) } =0
80 .ctors : { *(.ctors) }
81 .dtors : { *(.dtors) }
82
83 /* Read-write section, merged into data segment: */
84 . = (. + 0x00FF) & 0xFFFFFF00;
85 _erotext = .;
86 PROVIDE (erotext = .);
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]87 .reloc :
wdenkabf7a7c2003-12-08 01:34:36 +0000[diff] [blame]88 {
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]89 __got_start = .;
wdenkabf7a7c2003-12-08 01:34:36 +0000[diff] [blame]90 *(.got)
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]91 __got_end = .;
wdenkabf7a7c2003-12-08 01:34:36 +0000[diff] [blame]92 _GOT2_TABLE_ = .;
93 *(.got2)
94 _FIXUP_TABLE_ = .;
95 *(.fixup)
96 }
97 __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
98 __fixup_entries = (. - _FIXUP_TABLE_)>>2;
99
100 .data :
101 {
102 *(.data)
103 *(.data1)
104 *(.sdata)
105 *(.sdata2)
106 *(.dynamic)
107 CONSTRUCTORS
108 }
109 _edata = .;
110 PROVIDE (edata = .);
111
Wolfgang Denk5dd2c652005-08-31 12:28:00 +0200[diff] [blame]112 . = .;
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]113 __u_boot_cmd_start = .;
114 .u_boot_cmd : { *(.u_boot_cmd) }
115 __u_boot_cmd_end = .;
116
Wolfgang Denk5dd2c652005-08-31 12:28:00 +0200[diff] [blame]117 . = .;
wdenkabf7a7c2003-12-08 01:34:36 +0000[diff] [blame]118 __start___ex_table = .;
119 __ex_table : { *(__ex_table) }
120 __stop___ex_table = .;
121
122 . = ALIGN(256);
123 __init_begin = .;
124 .text.init : { *(.text.init) }
125 .data.init : { *(.data.init) }
126 . = ALIGN(256);
127 __init_end = .;
128
129 __bss_start = .;
Wolfgang Denk828a9782008-01-12 20:31:39 +0100[diff] [blame]130 .bss (NOLOAD) :
wdenkabf7a7c2003-12-08 01:34:36 +0000[diff] [blame]131 {
132 _sbss = .;
133 *(.sbss) *(.scommon)
134 *(.dynbss)
135 *(.bss)
136 *(COMMON)
137 . = ALIGN(4);
138 _ebss = .;
139 }
140 _end = . ;
141 PROVIDE (end = .);
142}