| Michael Trimarchi | e30a336 | 2008-11-28 13:22:09 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2005 freescale semiconductor |
| 3 | * Copyright (c) 2005 MontaVista Software |
| 4 | * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 19 | * MA 02111-1307 USA |
| 20 | */ |
| 21 | |
| 22 | #ifndef _EHCI_FSL_H |
| 23 | #define _EHCI_FSL_H |
| 24 | |
| 25 | /* Global offsets */ |
| 26 | #define FSL_SKIP_PCI 0x100 |
| 27 | |
| 28 | /* offsets for the non-ehci registers in the FSL SOC USB controller */ |
| 29 | #define FSL_SOC_USB_ULPIVP 0x170 |
| 30 | #define FSL_SOC_USB_PORTSC1 0x184 |
| 31 | #define PORT_PTS_MSK (3 << 30) |
| 32 | #define PORT_PTS_UTMI (0 << 30) |
| 33 | #define PORT_PTS_ULPI (2 << 30) |
| 34 | #define PORT_PTS_SERIAL (3 << 30) |
| 35 | #define PORT_PTS_PTW (1 << 28) |
| 36 | |
| 37 | /* USBMODE Register bits */ |
| 38 | #define CM_IDLE (0 << 0) |
| 39 | #define CM_RESERVED (1 << 0) |
| 40 | #define CM_DEVICE (2 << 0) |
| 41 | #define CM_HOST (3 << 0) |
| 42 | #define USBMODE_RESERVED_2 (0 << 2) |
| 43 | #define SLOM (1 << 3) |
| 44 | #define SDIS (1 << 4) |
| 45 | |
| 46 | /* CONTROL Register bits */ |
| 47 | #define ULPI_INT_EN (1 << 0) |
| 48 | #define WU_INT_EN (1 << 1) |
| 49 | #define USB_EN (1 << 2) |
| 50 | #define LSF_EN (1 << 3) |
| 51 | #define KEEP_OTG_ON (1 << 4) |
| 52 | #define OTG_PORT (1 << 5) |
| 53 | #define REFSEL_12MHZ (0 << 6) |
| 54 | #define REFSEL_16MHZ (1 << 6) |
| 55 | #define REFSEL_48MHZ (2 << 6) |
| 56 | #define PLL_RESET (1 << 8) |
| 57 | #define UTMI_PHY_EN (1 << 9) |
| 58 | #define PHY_CLK_SEL_UTMI (0 << 10) |
| 59 | #define PHY_CLK_SEL_ULPI (1 << 10) |
| 60 | #define CLKIN_SEL_USB_CLK (0 << 11) |
| 61 | #define CLKIN_SEL_USB_CLK2 (1 << 11) |
| 62 | #define CLKIN_SEL_SYS_CLK (2 << 11) |
| 63 | #define CLKIN_SEL_SYS_CLK2 (3 << 11) |
| 64 | #define RESERVED_18 (0 << 13) |
| 65 | #define RESERVED_17 (0 << 14) |
| 66 | #define RESERVED_16 (0 << 15) |
| 67 | #define WU_INT (1 << 16) |
| 68 | #define PHY_CLK_VALID (1 << 17) |
| 69 | |
| 70 | #define FSL_SOC_USB_PORTSC2 0x188 |
| 71 | #define FSL_SOC_USB_USBMODE 0x1a8 |
| 72 | #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */ |
| 73 | #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */ |
| 74 | #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */ |
| 75 | #define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */ |
| 76 | #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */ |
| 77 | #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */ |
| 78 | #define SNOOP_SIZE_2GB 0x1e |
| 79 | |
| 80 | /* System Clock Control Register */ |
| 81 | #define MPC83XX_SCCR_USB_MASK 0x00f00000 |
| 82 | #define MPC83XX_SCCR_USB_DRCM_11 0x00300000 |
| 83 | #define MPC83XX_SCCR_USB_DRCM_01 0x00100000 |
| 84 | #define MPC83XX_SCCR_USB_DRCM_10 0x00200000 |
| 85 | |
| 86 | #endif /* _EHCI_FSL_H */ |