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Vitaly Andrianov29646842015-09-19 16:26:40 +05301/*
2 * K2G EVM : Board initialization
3 *
4 * (C) Copyright 2015
5 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9#include <common.h>
10#include <asm/arch/clock.h>
Vitaly Andrianovcafc8f42015-09-19 16:26:52 +053011#include <asm/ti-common/keystone_net.h>
Roger Quadros44157de2015-09-19 16:26:53 +053012#include <asm/arch/psc_defs.h>
13#include <asm/arch/mmc_host_def.h>
Vitaly Andrianov680ec772015-09-19 16:26:45 +053014#include "mux-k2g.h"
Vitaly Andrianov29646842015-09-19 16:26:40 +053015
Vitaly Andrianov7fd5b642015-09-19 16:26:41 +053016#define SYS_CLK 24000000
17
18unsigned int external_clk[ext_clk_count] = {
19 [sys_clk] = SYS_CLK,
20 [pa_clk] = SYS_CLK,
21 [tetris_clk] = SYS_CLK,
22 [ddr3a_clk] = SYS_CLK,
23 [uart_clk] = SYS_CLK,
24};
25
Lokesh Vutla9027e082016-03-04 10:36:41 -060026static int arm_speeds[DEVSPEED_NUMSPDS] = {
27 SPD400,
28 SPD600,
29 SPD800,
30 SPD900,
31 SPD1000,
32 SPD900,
33 SPD800,
34 SPD600,
35 SPD400,
36 SPD200,
37};
38
39static int dev_speeds[DEVSPEED_NUMSPDS] = {
40 SPD600,
41 SPD800,
42 SPD900,
43 SPD1000,
44 SPD900,
45 SPD800,
46 SPD600,
47 SPD400,
48};
49
50static struct pll_init_data main_pll_config[NUM_SPDS] = {
51 [SPD400] = {MAIN_PLL, 100, 3, 2},
52 [SPD600] = {MAIN_PLL, 300, 6, 2},
53 [SPD800] = {MAIN_PLL, 200, 3, 2},
54 [SPD900] = {TETRIS_PLL, 75, 1, 2},
55 [SPD1000] = {TETRIS_PLL, 250, 3, 2},
56};
57
58static struct pll_init_data tetris_pll_config[NUM_SPDS] = {
59 [SPD200] = {TETRIS_PLL, 250, 3, 10},
60 [SPD400] = {TETRIS_PLL, 100, 1, 6},
61 [SPD600] = {TETRIS_PLL, 100, 1, 4},
62 [SPD800] = {TETRIS_PLL, 400, 3, 4},
63 [SPD900] = {TETRIS_PLL, 75, 1, 2},
64 [SPD1000] = {TETRIS_PLL, 250, 3, 2},
65};
66
Vitaly Andrianov29646842015-09-19 16:26:40 +053067static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
68static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2};
Vitaly Andrianovbbf8ac22015-09-19 16:26:43 +053069static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10};
Vitaly Andrianov29646842015-09-19 16:26:40 +053070
71struct pll_init_data *get_pll_init_data(int pll)
72{
Lokesh Vutla9027e082016-03-04 10:36:41 -060073 int speed;
Vitaly Andrianov29646842015-09-19 16:26:40 +053074 struct pll_init_data *data = NULL;
75
76 switch (pll) {
77 case MAIN_PLL:
Lokesh Vutla9027e082016-03-04 10:36:41 -060078 speed = get_max_dev_speed(dev_speeds);
79 data = &main_pll_config[speed];
Vitaly Andrianov29646842015-09-19 16:26:40 +053080 break;
81 case TETRIS_PLL:
Lokesh Vutla9027e082016-03-04 10:36:41 -060082 speed = get_max_arm_speed(arm_speeds);
83 data = &tetris_pll_config[speed];
Vitaly Andrianov29646842015-09-19 16:26:40 +053084 break;
85 case NSS_PLL:
86 data = &nss_pll_config;
87 break;
88 case UART_PLL:
89 data = &uart_pll_config;
90 break;
91 case DDR3_PLL:
Vitaly Andrianovbbf8ac22015-09-19 16:26:43 +053092 data = &ddr3_pll_config;
Vitaly Andrianov29646842015-09-19 16:26:40 +053093 break;
94 default:
95 data = NULL;
96 }
97
98 return data;
99}
100
101s16 divn_val[16] = {
102 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
103};
104
Roger Quadros44157de2015-09-19 16:26:53 +0530105#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
106int board_mmc_init(bd_t *bis)
107{
108 if (psc_enable_module(KS2_LPSC_MMC)) {
109 printf("%s module enabled failed\n", __func__);
110 return -1;
111 }
112
113 omap_mmc_init(0, 0, 0, -1, -1);
114 omap_mmc_init(1, 0, 0, -1, -1);
115 return 0;
116}
117#endif
118
Vitaly Andrianov29646842015-09-19 16:26:40 +0530119#ifdef CONFIG_BOARD_EARLY_INIT_F
120int board_early_init_f(void)
121{
122 init_plls();
123
Vitaly Andrianov680ec772015-09-19 16:26:45 +0530124 k2g_mux_config();
125
Lokesh Vutlabd46e0e2015-09-19 16:26:54 +0530126 /* deassert FLASH_HOLD */
127 clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
128 BIT(9));
129 setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
130 BIT(9));
131
Vitaly Andrianov29646842015-09-19 16:26:40 +0530132 return 0;
133}
134#endif
135
136#ifdef CONFIG_SPL_BUILD
137void spl_init_keystone_plls(void)
138{
139 init_plls();
140}
141#endif
Vitaly Andrianovcafc8f42015-09-19 16:26:52 +0530142
143#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
144struct eth_priv_t eth_priv_cfg[] = {
145 {
146 .int_name = "K2G_EMAC",
147 .rx_flow = 0,
148 .phy_addr = 0,
149 .slave_port = 1,
150 .sgmii_link_type = SGMII_LINK_MAC_PHY,
151 .phy_if = PHY_INTERFACE_MODE_RGMII,
152 },
153};
154
155int get_num_eth_ports(void)
156{
157 return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
158}
159#endif