Blame - board/amcc/katmai/katmai.c - filogic/uboot

2007-02-20 10:57:08 +0100

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/*

Stefan Roese

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2009-11-12 12:00:49 +0100

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Stefan Roese

2007-02-20 10:57:08 +0100

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* Stefan Roese, DENX Software Engineering, sr@denx.de.

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*

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* See file CREDITS for list of people who contributed to this

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* project.

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*

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* This program is free software; you can redistribute it and/or

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* modify it under the terms of the GNU General Public License as

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* published by the Free Software Foundation; either version 2 of

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* the License, or (at your option) any later version.

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*

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* This program is distributed in the hope that it will be useful,

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* GNU General Public License for more details.

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*

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* You should have received a copy of the GNU General Public License

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* along with this program; if not, write to the Free Software

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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,

* MA 02111-1307 USA

*

*/

#include <common.h>

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#include <asm/ppc4xx.h>

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#include <i2c.h>

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#include <libfdt.h>

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#include <fdt_support.h>

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#include <netdev.h>

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#include <asm/processor.h>

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#include <asm/io.h>

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#include <asm/ppc4xx-gpio.h>

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#include <asm/4xx_pcie.h>

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#include <asm/errno.h>

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Wolfgang Denk

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DECLARE_GLOBAL_DATA_PTR;

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Stefan Roese

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int board_early_init_f (void)

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{

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unsigned long mfr;

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/*----------------------------------------------------------------------+

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* Interrupt controller setup for the Katmai 440SPe Evaluation board.

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*-----------------------------------------------------------------------+

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*-----------------------------------------------------------------------+

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*-----------+-----------------------------------+-------+-------+-------+

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* IRQ 02 | IIC0 | High | Level | Non |

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* IRQ 03 | IIC1 | High | Level | Non |

* IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non |

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* IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non |

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* IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit |

* IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non |

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* IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit |

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* IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non |

* IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non |

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* IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. |

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*------------------------------------------------------------------------

* IRQ 63 | XOR | High | Level | Non |

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*-----------------------------------------------------------------------

* IRQ 71 | Reserved | N/A | N/A | Non |

* IRQ 79 | Reserved | N/A | N/A | Non |

* IRQ 87 | Reserved | N/A | N/A | Non |

* IRQ 94 | Reserved | N/A | N/A | Non |

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* IRQ 95 | Reserved | N/A | N/A | Non |

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*-----------------------------------------------------------------------

*-----------+-----------------------------------+-------+-------+-------+ */

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/*-------------------------------------------------------------------------+

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* Put UICs in PowerPC440SPemode.

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* Initialise UIC registers. Clear all interrupts. Disable all interrupts.

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* Set critical interrupt values. Set interrupt polarities. Set interrupt

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* trigger levels. Make bit 0 High priority. Clear all interrupts again.

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*------------------------------------------------------------------------*/

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mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */

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mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */

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mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical interrupts: */

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mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/

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mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */

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mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */

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mtdcr (UIC3SR, 0x00000000); /* clear all interrupts*/

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mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts*/

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mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */

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mtdcr (UIC2ER, 0x00000000); /* disable all interrupts*/

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mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts*/

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mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/

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mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */

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mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */

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mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */

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mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */

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mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts*/

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mtdcr (UIC1ER, 0x00000000); /* disable all interrupts*/

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mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts*/

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mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */

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mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/

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mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */

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mtdcr (UIC1SR, 0x00000000); /* clear all interrupts*/

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mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts*/

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mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */

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mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted cascade to be checked */

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mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical interrupts*/

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mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/

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mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */

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mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */

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mtdcr (UIC0SR, 0x00000000); /* clear all interrupts*/

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mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts*/

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mfsdr(SDR0_MFR, mfr);

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mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */

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mtsdr(SDR0_MFR, mfr);

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Jean-Christophe PLAGNIOL-VILLARD

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mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0);

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out32(GPIO0_OR, CONFIG_SYS_GPIO_OR);

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out32(GPIO0_ODR, CONFIG_SYS_GPIO_ODR);

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out32(GPIO0_TCR, CONFIG_SYS_GPIO_TCR);

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return 0;

}

int checkboard (void)

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{

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char buf[64];

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int i = getenv_f("serial#", buf, sizeof(buf));

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printf("Board: Katmai - AMCC 440SPe Evaluation Board");

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if (i > 0) {

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puts(", serial# ");

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puts(buf);

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}

putc('\n');

return 0;

}

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/*

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* Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with

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* board specific values.

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*/

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u32 ddr_wrdtr(u32 default_val) {

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return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);

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}

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u32 ddr_clktr(u32 default_val) {

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return (SDRAM_CLKTR_CLKP_90_DEG_ADV);

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}

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#if defined(CONFIG_PCI)

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int board_pcie_card_present(int port)

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{

u32 val;

val = in32(GPIO0_IR);

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switch (port) {

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case 0:

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return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0));

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case 1:

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return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1));

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case 2:

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return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2));

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default:

return 0;

}

}

Stefan Roese