Tom Warren | 7a3fa01 | 2013-01-28 13:32:13 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, |
| 6 | * version 2, as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 15 | */ |
| 16 | |
| 17 | #ifndef _PINMUX_CONFIG_DALMORE_H_ |
| 18 | #define _PINMUX_CONFIG_DALMORE_H_ |
| 19 | |
| 20 | #define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \ |
| 21 | { \ |
| 22 | .pingroup = PINGRP_##_pingroup, \ |
| 23 | .func = PMUX_FUNC_##_mux, \ |
| 24 | .pull = PMUX_PULL_##_pull, \ |
| 25 | .tristate = PMUX_TRI_##_tri, \ |
| 26 | .io = PMUX_PIN_##_io, \ |
| 27 | .lock = PMUX_PIN_LOCK_DEFAULT, \ |
| 28 | .od = PMUX_PIN_OD_DEFAULT, \ |
| 29 | .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ |
| 30 | } |
| 31 | |
| 32 | #define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \ |
| 33 | { \ |
| 34 | .pingroup = PINGRP_##_pingroup, \ |
| 35 | .func = PMUX_FUNC_##_mux, \ |
| 36 | .pull = PMUX_PULL_##_pull, \ |
| 37 | .tristate = PMUX_TRI_##_tri, \ |
| 38 | .io = PMUX_PIN_##_io, \ |
| 39 | .lock = PMUX_PIN_LOCK_##_lock, \ |
| 40 | .od = PMUX_PIN_OD_##_od, \ |
| 41 | .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ |
| 42 | } |
| 43 | |
| 44 | #define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \ |
| 45 | { \ |
| 46 | .pingroup = PINGRP_##_pingroup, \ |
| 47 | .func = PMUX_FUNC_##_mux, \ |
| 48 | .pull = PMUX_PULL_##_pull, \ |
| 49 | .tristate = PMUX_TRI_##_tri, \ |
| 50 | .io = PMUX_PIN_##_io, \ |
| 51 | .lock = PMUX_PIN_LOCK_##_lock, \ |
| 52 | .od = PMUX_PIN_OD_DEFAULT, \ |
| 53 | .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ |
| 54 | } |
| 55 | |
| 56 | static struct pingroup_config tegra114_pinmux_common[] = { |
| 57 | /* SDMMC1 pinmux */ |
| 58 | DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT), |
| 59 | DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT), |
| 60 | DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT), |
| 61 | DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT), |
| 62 | DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT), |
| 63 | DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT), |
| 64 | DEFAULT_PINMUX(SDMMC1_WP_N, SDMMC1, UP, NORMAL, INPUT), |
| 65 | |
| 66 | /* SDMMC3 pinmux */ |
| 67 | DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT), |
| 68 | DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3, NORMAL, NORMAL, INPUT), |
| 69 | DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3, NORMAL, NORMAL, OUTPUT), |
| 70 | |
| 71 | DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT), |
| 72 | DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT), |
| 73 | DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT), |
| 74 | DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT), |
| 75 | DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT), |
| 76 | DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT), |
| 77 | |
| 78 | /* SDMMC4 pinmux */ |
| 79 | LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), |
| 80 | LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), |
| 81 | LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), |
| 82 | LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), |
| 83 | LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), |
| 84 | LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), |
| 85 | LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), |
| 86 | LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), |
| 87 | LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), |
| 88 | LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), |
| 89 | LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE), |
| 90 | |
| 91 | /* I2C1 pinmux */ |
| 92 | I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
| 93 | I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
| 94 | |
| 95 | /* I2C2 pinmux */ |
| 96 | I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
| 97 | I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
| 98 | |
| 99 | /* I2C3 pinmux */ |
| 100 | I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
| 101 | I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
| 102 | |
| 103 | /* I2C4 pinmux */ |
| 104 | I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
| 105 | I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
| 106 | |
| 107 | /* Power I2C pinmux */ |
| 108 | I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
| 109 | I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
| 110 | |
| 111 | DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT), |
| 112 | DEFAULT_PINMUX(ULPI_DATA1, UARTA, UP, NORMAL, INPUT), |
| 113 | DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT), |
| 114 | DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, INPUT), |
| 115 | |
| 116 | DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT), |
| 117 | DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT), |
| 118 | DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT), |
| 119 | DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, OUTPUT), |
| 120 | DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT), |
| 121 | DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT), |
| 122 | DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT), |
| 123 | DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT), |
| 124 | DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT), |
| 125 | DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT), |
| 126 | DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT), |
| 127 | DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), |
| 128 | DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT), |
| 129 | DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT), |
| 130 | DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, NORMAL, INPUT), |
| 131 | DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT), |
| 132 | DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT), |
| 133 | DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT), |
| 134 | DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT), |
| 135 | DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT), |
| 136 | DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT), |
| 137 | DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT), |
| 138 | DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT), |
| 139 | DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, OUTPUT), |
| 140 | DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT), |
| 141 | DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT), |
| 142 | DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT), |
| 143 | DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, OUTPUT), |
| 144 | DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT), |
| 145 | DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT), |
| 146 | DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT), |
| 147 | DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT), |
| 148 | DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT), |
| 149 | DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT), |
| 150 | DEFAULT_PINMUX(CLK3_REQ, DEV3, NORMAL, NORMAL, INPUT), |
| 151 | DEFAULT_PINMUX(GMI_WP_N, GMI, NORMAL, NORMAL, INPUT), |
| 152 | DEFAULT_PINMUX(GMI_CS2_N, RSVD1, UP, NORMAL, INPUT), |
| 153 | DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT), |
| 154 | DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT), |
| 155 | DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT), |
| 156 | DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, NORMAL, INPUT), |
| 157 | DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, NORMAL, INPUT), |
| 158 | DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT), |
| 159 | DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, UP, NORMAL, INPUT), |
| 160 | DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT), |
| 161 | DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT), |
| 162 | DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT), |
| 163 | DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, INPUT), |
| 164 | DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, INPUT), |
| 165 | DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT), |
| 166 | DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT), |
| 167 | DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT), |
| 168 | |
| 169 | /* KBC keys */ |
| 170 | DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT), |
| 171 | DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT), |
| 172 | DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT), |
| 173 | DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT), |
| 174 | DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT), |
| 175 | DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT), |
| 176 | DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT), |
| 177 | DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT), |
| 178 | DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT), |
| 179 | DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT), |
| 180 | DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT), |
| 181 | DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT), |
| 182 | DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT), |
| 183 | DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT), |
| 184 | DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT), |
| 185 | DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT), |
| 186 | DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT), |
| 187 | DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT), |
| 188 | DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT), |
| 189 | DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT), |
| 190 | DEFAULT_PINMUX(GPIO_PV1, RSVD1, UP, NORMAL, INPUT), |
| 191 | |
| 192 | DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT), |
| 193 | DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT), |
| 194 | DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), |
| 195 | DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT), |
| 196 | DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT), |
| 197 | DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT), |
| 198 | DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT), |
| 199 | DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT), |
| 200 | DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT), |
| 201 | DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT), |
| 202 | DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT), |
| 203 | DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT), |
| 204 | DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT), |
| 205 | DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT), |
| 206 | DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT), |
| 207 | |
| 208 | DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT), |
| 209 | DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT), |
| 210 | DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT), |
| 211 | DEFAULT_PINMUX(SPI1_CS1_N, SPI1, NORMAL, NORMAL, INPUT), |
| 212 | DEFAULT_PINMUX(SPI1_CS2_N, SPI1, NORMAL, NORMAL, INPUT), |
| 213 | DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT), |
| 214 | DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT), |
| 215 | DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT), |
| 216 | |
| 217 | /* GPIOs */ |
| 218 | /* SDMMC1 CD gpio */ |
| 219 | DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT), |
| 220 | |
| 221 | /* Touch RESET */ |
| 222 | DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, OUTPUT), |
| 223 | |
| 224 | /* Power rails GPIO */ |
| 225 | DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, NORMAL, INPUT), |
| 226 | DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT), |
| 227 | DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT), |
| 228 | }; |
| 229 | |
| 230 | static struct pingroup_config unused_pins_lowpower[] = { |
| 231 | DEFAULT_PINMUX(GMI_CS0_N, NAND, UP, TRISTATE, OUTPUT), |
| 232 | DEFAULT_PINMUX(GMI_CS3_N, NAND, UP, TRISTATE, OUTPUT), |
| 233 | DEFAULT_PINMUX(GMI_CS4_N, NAND, UP, TRISTATE, OUTPUT), |
| 234 | DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT), |
| 235 | DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, INPUT), |
| 236 | DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, INPUT), |
| 237 | DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, INPUT), |
| 238 | DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, INPUT), |
| 239 | DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, INPUT), |
| 240 | DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, INPUT), |
| 241 | DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, INPUT), |
| 242 | DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, INPUT), |
| 243 | DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, TRISTATE, OUTPUT), |
| 244 | DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, TRISTATE, OUTPUT), |
| 245 | DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT), |
| 246 | DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT), |
| 247 | }; |
| 248 | |
| 249 | #endif /* _PINMUX_CONFIG_DALMORE_H_ */ |