Stefan Roese | 6edf27e | 2016-05-17 15:04:16 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2016 Stefan Roese <sr@denx.de> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Konstantin Porotchkin | f4d32b4 | 2017-02-16 13:52:29 +0200 | [diff] [blame] | 8 | #include <dm.h> |
Stefan Roese | 6edf27e | 2016-05-17 15:04:16 +0200 | [diff] [blame] | 9 | #include <i2c.h> |
Konstantin Porotchkin | f4d32b4 | 2017-02-16 13:52:29 +0200 | [diff] [blame] | 10 | #include <phy.h> |
Stefan Roese | 6edf27e | 2016-05-17 15:04:16 +0200 | [diff] [blame] | 11 | #include <asm/io.h> |
| 12 | #include <asm/arch/cpu.h> |
| 13 | #include <asm/arch/soc.h> |
| 14 | |
| 15 | DECLARE_GLOBAL_DATA_PTR; |
| 16 | |
| 17 | /* IO expander I2C device */ |
| 18 | #define I2C_IO_EXP_ADDR 0x22 |
| 19 | #define I2C_IO_CFG_REG_0 0x6 |
| 20 | #define I2C_IO_DATA_OUT_REG_0 0x2 |
| 21 | #define I2C_IO_REG_0_SATA_OFF 2 |
| 22 | #define I2C_IO_REG_0_USB_H_OFF 1 |
| 23 | |
Konstantin Porotchkin | b65ffc4 | 2017-02-16 13:52:32 +0200 | [diff] [blame] | 24 | /* The pin control values are the same for DB and Espressobin */ |
Konstantin Porotchkin | cfa88a3 | 2017-02-16 13:52:26 +0200 | [diff] [blame] | 25 | #define PINCTRL_NB_REG_VALUE 0x000173fa |
| 26 | #define PINCTRL_SB_REG_VALUE 0x00007a23 |
| 27 | |
Konstantin Porotchkin | f4d32b4 | 2017-02-16 13:52:29 +0200 | [diff] [blame] | 28 | /* Ethernet switch registers */ |
| 29 | /* SMI addresses for multi-chip mode */ |
| 30 | #define MVEBU_PORT_CTRL_SMI_ADDR(p) (16 + (p)) |
| 31 | #define MVEBU_SW_G2_SMI_ADDR (28) |
| 32 | |
| 33 | /* Multi-chip mode */ |
| 34 | #define MVEBU_SW_SMI_DATA_REG (1) |
| 35 | #define MVEBU_SW_SMI_CMD_REG (0) |
| 36 | #define SW_SMI_CMD_REG_ADDR_OFF 0 |
| 37 | #define SW_SMI_CMD_DEV_ADDR_OFF 5 |
| 38 | #define SW_SMI_CMD_SMI_OP_OFF 10 |
| 39 | #define SW_SMI_CMD_SMI_MODE_OFF 12 |
| 40 | #define SW_SMI_CMD_SMI_BUSY_OFF 15 |
| 41 | |
| 42 | /* Single-chip mode */ |
| 43 | /* Switch Port Registers */ |
| 44 | #define MVEBU_SW_LINK_CTRL_REG (1) |
| 45 | #define MVEBU_SW_PORT_CTRL_REG (4) |
| 46 | |
| 47 | /* Global 2 Registers */ |
| 48 | #define MVEBU_G2_SMI_PHY_CMD_REG (24) |
| 49 | #define MVEBU_G2_SMI_PHY_DATA_REG (25) |
| 50 | |
Stefan Roese | 6edf27e | 2016-05-17 15:04:16 +0200 | [diff] [blame] | 51 | int board_early_init_f(void) |
| 52 | { |
Konstantin Porotchkin | cfa88a3 | 2017-02-16 13:52:26 +0200 | [diff] [blame] | 53 | const void *blob = gd->fdt_blob; |
| 54 | const char *bank_name; |
| 55 | const char *compat = "marvell,armada-3700-pinctl"; |
| 56 | int off, len; |
| 57 | void __iomem *addr; |
| 58 | |
| 59 | /* FIXME |
| 60 | * Temporary WA for setting correct pin control values |
| 61 | * until the real pin control driver is awailable. |
| 62 | */ |
| 63 | off = fdt_node_offset_by_compatible(blob, -1, compat); |
| 64 | while (off != -FDT_ERR_NOTFOUND) { |
| 65 | bank_name = fdt_getprop(blob, off, "bank-name", &len); |
| 66 | addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent( |
| 67 | blob, off, "reg", 0, NULL, true); |
| 68 | if (!strncmp(bank_name, "armada-3700-nb", len)) |
| 69 | writel(PINCTRL_NB_REG_VALUE, addr); |
| 70 | else if (!strncmp(bank_name, "armada-3700-sb", len)) |
| 71 | writel(PINCTRL_SB_REG_VALUE, addr); |
| 72 | |
| 73 | off = fdt_node_offset_by_compatible(blob, off, compat); |
| 74 | } |
Stefan Roese | 6edf27e | 2016-05-17 15:04:16 +0200 | [diff] [blame] | 75 | |
| 76 | return 0; |
| 77 | } |
| 78 | |
| 79 | int board_init(void) |
| 80 | { |
| 81 | /* adress of boot parameters */ |
| 82 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
| 83 | |
| 84 | return 0; |
| 85 | } |
| 86 | |
| 87 | /* Board specific AHCI / SATA enable code */ |
| 88 | int board_ahci_enable(void) |
| 89 | { |
| 90 | struct udevice *dev; |
| 91 | int ret; |
| 92 | u8 buf[8]; |
| 93 | |
Konstantin Porotchkin | b65ffc4 | 2017-02-16 13:52:32 +0200 | [diff] [blame] | 94 | /* Only DB requres this configuration */ |
| 95 | if (!of_machine_is_compatible("marvell,armada-3720-db")) |
| 96 | return 0; |
| 97 | |
Stefan Roese | 6edf27e | 2016-05-17 15:04:16 +0200 | [diff] [blame] | 98 | /* Configure IO exander PCA9555: 7bit address 0x22 */ |
| 99 | ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev); |
| 100 | if (ret) { |
| 101 | printf("Cannot find PCA9555: %d\n", ret); |
| 102 | return 0; |
| 103 | } |
| 104 | |
| 105 | ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1); |
| 106 | if (ret) { |
| 107 | printf("Failed to read IO expander value via I2C\n"); |
| 108 | return -EIO; |
| 109 | } |
| 110 | |
| 111 | /* |
| 112 | * Enable SATA power via IO expander connected via I2C by setting |
| 113 | * the corresponding bit to output mode to enable power for SATA |
| 114 | */ |
| 115 | buf[0] &= ~(1 << I2C_IO_REG_0_SATA_OFF); |
| 116 | ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1); |
| 117 | if (ret) { |
| 118 | printf("Failed to set IO expander via I2C\n"); |
| 119 | return -EIO; |
| 120 | } |
| 121 | |
| 122 | return 0; |
| 123 | } |
| 124 | |
| 125 | /* Board specific xHCI enable code */ |
Jon Nettleton | a81f47c | 2017-11-06 10:33:19 +0200 | [diff] [blame] | 126 | int board_xhci_enable(fdt_addr_t base) |
Stefan Roese | 6edf27e | 2016-05-17 15:04:16 +0200 | [diff] [blame] | 127 | { |
| 128 | struct udevice *dev; |
| 129 | int ret; |
| 130 | u8 buf[8]; |
| 131 | |
Konstantin Porotchkin | b65ffc4 | 2017-02-16 13:52:32 +0200 | [diff] [blame] | 132 | /* Only DB requres this configuration */ |
| 133 | if (!of_machine_is_compatible("marvell,armada-3720-db")) |
| 134 | return 0; |
| 135 | |
Stefan Roese | 6edf27e | 2016-05-17 15:04:16 +0200 | [diff] [blame] | 136 | /* Configure IO exander PCA9555: 7bit address 0x22 */ |
| 137 | ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev); |
| 138 | if (ret) { |
| 139 | printf("Cannot find PCA9555: %d\n", ret); |
| 140 | return 0; |
| 141 | } |
| 142 | |
| 143 | printf("Enable USB VBUS\n"); |
| 144 | |
| 145 | /* |
| 146 | * Read configuration (direction) and set VBUS pin as output |
| 147 | * (reset pin = output) |
| 148 | */ |
| 149 | ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1); |
| 150 | if (ret) { |
| 151 | printf("Failed to read IO expander value via I2C\n"); |
| 152 | return -EIO; |
| 153 | } |
| 154 | buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF); |
| 155 | ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1); |
| 156 | if (ret) { |
| 157 | printf("Failed to set IO expander via I2C\n"); |
| 158 | return -EIO; |
| 159 | } |
| 160 | |
| 161 | /* Read VBUS output value and disable it */ |
| 162 | ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1); |
| 163 | if (ret) { |
| 164 | printf("Failed to read IO expander value via I2C\n"); |
| 165 | return -EIO; |
| 166 | } |
| 167 | buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF); |
| 168 | ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1); |
| 169 | if (ret) { |
| 170 | printf("Failed to set IO expander via I2C\n"); |
| 171 | return -EIO; |
| 172 | } |
| 173 | |
| 174 | /* |
| 175 | * Required delay for configuration to settle - must wait for |
| 176 | * power on port is disabled in case VBUS signal was high, |
| 177 | * required 3 seconds delay to let VBUS signal fully settle down |
| 178 | */ |
| 179 | mdelay(3000); |
| 180 | |
| 181 | /* Enable VBUS power: Set output value of VBUS pin as enabled */ |
| 182 | buf[0] |= (1 << I2C_IO_REG_0_USB_H_OFF); |
| 183 | ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1); |
| 184 | if (ret) { |
| 185 | printf("Failed to set IO expander via I2C\n"); |
| 186 | return -EIO; |
| 187 | } |
| 188 | |
| 189 | mdelay(500); /* required delay to let output value settle */ |
| 190 | |
| 191 | return 0; |
| 192 | } |
Konstantin Porotchkin | f4d32b4 | 2017-02-16 13:52:29 +0200 | [diff] [blame] | 193 | |
| 194 | /* Helper function for accessing switch devices in multi-chip connection mode */ |
| 195 | static int mii_multi_chip_mode_write(struct mii_dev *bus, int dev_smi_addr, |
| 196 | int smi_addr, int reg, u16 value) |
| 197 | { |
| 198 | u16 smi_cmd = 0; |
| 199 | |
| 200 | if (bus->write(bus, dev_smi_addr, 0, |
| 201 | MVEBU_SW_SMI_DATA_REG, value) != 0) { |
| 202 | printf("Error writing to the PHY addr=%02x reg=%02x\n", |
| 203 | smi_addr, reg); |
| 204 | return -EFAULT; |
| 205 | } |
| 206 | |
| 207 | smi_cmd = (1 << SW_SMI_CMD_SMI_BUSY_OFF) | |
| 208 | (1 << SW_SMI_CMD_SMI_MODE_OFF) | |
| 209 | (1 << SW_SMI_CMD_SMI_OP_OFF) | |
| 210 | (smi_addr << SW_SMI_CMD_DEV_ADDR_OFF) | |
| 211 | (reg << SW_SMI_CMD_REG_ADDR_OFF); |
| 212 | if (bus->write(bus, dev_smi_addr, 0, |
| 213 | MVEBU_SW_SMI_CMD_REG, smi_cmd) != 0) { |
| 214 | printf("Error writing to the PHY addr=%02x reg=%02x\n", |
| 215 | smi_addr, reg); |
| 216 | return -EFAULT; |
| 217 | } |
| 218 | |
| 219 | return 0; |
| 220 | } |
| 221 | |
| 222 | /* Bring-up board-specific network stuff */ |
| 223 | int board_network_enable(struct mii_dev *bus) |
| 224 | { |
| 225 | if (!of_machine_is_compatible("marvell,armada-3720-espressobin")) |
| 226 | return 0; |
| 227 | |
| 228 | /* |
| 229 | * FIXME: remove this code once Topaz driver gets available |
| 230 | * A3720 Community Board Only |
| 231 | * Configure Topaz switch (88E6341) |
| 232 | * Set port 0,1,2,3 to forwarding Mode (through Switch Port registers) |
| 233 | */ |
| 234 | mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0), |
| 235 | MVEBU_SW_PORT_CTRL_REG, 0x7f); |
| 236 | mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1), |
| 237 | MVEBU_SW_PORT_CTRL_REG, 0x7f); |
| 238 | mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2), |
| 239 | MVEBU_SW_PORT_CTRL_REG, 0x7f); |
| 240 | mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3), |
| 241 | MVEBU_SW_PORT_CTRL_REG, 0x7f); |
| 242 | |
| 243 | /* RGMII Delay on Port 0 (CPU port), force link to 1000Mbps */ |
| 244 | mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0), |
| 245 | MVEBU_SW_LINK_CTRL_REG, 0xe002); |
| 246 | |
| 247 | /* Power up PHY 1, 2, 3 (through Global 2 registers) */ |
| 248 | mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR, |
| 249 | MVEBU_G2_SMI_PHY_DATA_REG, 0x1140); |
| 250 | mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR, |
| 251 | MVEBU_G2_SMI_PHY_CMD_REG, 0x9620); |
| 252 | mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR, |
| 253 | MVEBU_G2_SMI_PHY_CMD_REG, 0x9640); |
| 254 | mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR, |
| 255 | MVEBU_G2_SMI_PHY_CMD_REG, 0x9660); |
| 256 | |
| 257 | return 0; |
| 258 | } |