Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Lokesh Vutla | 40700ad | 2013-02-12 21:29:08 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2013 |
| 4 | * Texas Instruments Incorporated, <www.ti.com> |
| 5 | * |
| 6 | * Lokesh Vutla <lokeshvutla@ti.com> |
| 7 | * |
| 8 | * Based on previous work by: |
| 9 | * Aneesh V <aneesh@ti.com> |
| 10 | * Steve Sakoman <steve@sakoman.com> |
Lokesh Vutla | 40700ad | 2013-02-12 21:29:08 +0000 | [diff] [blame] | 11 | */ |
| 12 | #include <common.h> |
Simon Glass | 79fd214 | 2019-08-01 09:46:43 -0600 | [diff] [blame] | 13 | #include <env.h> |
Simon Glass | a7b5130 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 14 | #include <init.h> |
Nishanth Menon | 627612c | 2013-03-26 05:20:54 +0000 | [diff] [blame] | 15 | #include <palmas.h> |
Dan Murphy | 57f29ab | 2014-02-03 06:59:02 -0600 | [diff] [blame] | 16 | #include <sata.h> |
Simon Glass | 3673618 | 2019-11-14 12:57:24 -0700 | [diff] [blame] | 17 | #include <serial.h> |
Lokesh Vutla | 3c7dc01 | 2016-03-08 09:18:05 +0530 | [diff] [blame] | 18 | #include <linux/string.h> |
Lokesh Vutla | be86f0e | 2014-08-04 19:42:24 +0530 | [diff] [blame] | 19 | #include <asm/gpio.h> |
Kishon Vijay Abraham I | ce61fd7 | 2015-02-23 18:40:19 +0530 | [diff] [blame] | 20 | #include <usb.h> |
| 21 | #include <linux/usb/gadget.h> |
Andreas Dannenberg | 5cf344b | 2016-06-27 09:19:22 -0500 | [diff] [blame] | 22 | #include <asm/omap_common.h> |
| 23 | #include <asm/omap_sec_common.h> |
Lokesh Vutla | be86f0e | 2014-08-04 19:42:24 +0530 | [diff] [blame] | 24 | #include <asm/arch/gpio.h> |
Lokesh Vutla | 1fd8022 | 2015-06-04 16:42:38 +0530 | [diff] [blame] | 25 | #include <asm/arch/dra7xx_iodelay.h> |
Lokesh Vutla | 41963ee | 2016-03-08 09:18:06 +0530 | [diff] [blame] | 26 | #include <asm/emif.h> |
Lokesh Vutla | 40700ad | 2013-02-12 21:29:08 +0000 | [diff] [blame] | 27 | #include <asm/arch/sys_proto.h> |
| 28 | #include <asm/arch/mmc_host_def.h> |
Roger Quadros | f019ee8 | 2013-11-11 16:56:44 +0200 | [diff] [blame] | 29 | #include <asm/arch/sata.h> |
Kishon Vijay Abraham I | ce61fd7 | 2015-02-23 18:40:19 +0530 | [diff] [blame] | 30 | #include <dwc3-uboot.h> |
| 31 | #include <dwc3-omap-uboot.h> |
Franklin S Cooper Jr | 236fca8 | 2019-02-27 13:29:36 +0530 | [diff] [blame] | 32 | #include <i2c.h> |
Kishon Vijay Abraham I | ce61fd7 | 2015-02-23 18:40:19 +0530 | [diff] [blame] | 33 | #include <ti-usb-phy-uboot.h> |
Dan Murphy | b1941f3 | 2016-03-30 12:58:37 -0500 | [diff] [blame] | 34 | #include <miiphy.h> |
Lokesh Vutla | 40700ad | 2013-02-12 21:29:08 +0000 | [diff] [blame] | 35 | |
| 36 | #include "mux_data.h" |
Lokesh Vutla | 3c7dc01 | 2016-03-08 09:18:05 +0530 | [diff] [blame] | 37 | #include "../common/board_detect.h" |
| 38 | |
Lokesh Vutla | 1337613 | 2017-08-21 12:50:53 +0530 | [diff] [blame] | 39 | #define board_is_dra76x_evm() board_ti_is("DRA76/7x") |
Lokesh Vutla | 3c7dc01 | 2016-03-08 09:18:05 +0530 | [diff] [blame] | 40 | #define board_is_dra74x_evm() board_ti_is("5777xCPU") |
Ravi Babu | e103108 | 2016-03-15 18:09:14 -0500 | [diff] [blame] | 41 | #define board_is_dra72x_evm() board_ti_is("DRA72x-T") |
Lokesh Vutla | b9d8f8e | 2016-11-23 13:25:24 +0530 | [diff] [blame] | 42 | #define board_is_dra71x_evm() board_ti_is("DRA79x,D") |
Mugunthan V N | 3a7f10c | 2016-09-27 13:01:42 +0530 | [diff] [blame] | 43 | #define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \ |
| 44 | (strncmp("H", board_ti_get_rev(), 1) <= 0)) |
| 45 | #define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \ |
| 46 | (strncmp("C", board_ti_get_rev(), 1) <= 0)) |
Lokesh Vutla | b85fbcd | 2016-03-08 09:18:08 +0530 | [diff] [blame] | 47 | #define board_ti_get_emif_size() board_ti_get_emif1_size() + \ |
| 48 | board_ti_get_emif2_size() |
Lokesh Vutla | 40700ad | 2013-02-12 21:29:08 +0000 | [diff] [blame] | 49 | |
Mugunthan V N | ab48f78 | 2013-07-08 16:04:41 +0530 | [diff] [blame] | 50 | #ifdef CONFIG_DRIVER_TI_CPSW |
| 51 | #include <cpsw.h> |
| 52 | #endif |
| 53 | |
Lokesh Vutla | 40700ad | 2013-02-12 21:29:08 +0000 | [diff] [blame] | 54 | DECLARE_GLOBAL_DATA_PTR; |
| 55 | |
Lokesh Vutla | be86f0e | 2014-08-04 19:42:24 +0530 | [diff] [blame] | 56 | /* GPIO 7_11 */ |
| 57 | #define GPIO_DDR_VTT_EN 203 |
| 58 | |
Lokesh Vutla | 3c7dc01 | 2016-03-08 09:18:05 +0530 | [diff] [blame] | 59 | #define SYSINFO_BOARD_NAME_MAX_LEN 37 |
| 60 | |
Franklin S Cooper Jr | 236fca8 | 2019-02-27 13:29:36 +0530 | [diff] [blame] | 61 | /* I2C I/O Expander */ |
| 62 | #define NAND_PCF8575_ADDR 0x21 |
| 63 | #define NAND_PCF8575_I2C_BUS_NUM 0 |
| 64 | |
Lokesh Vutla | 40700ad | 2013-02-12 21:29:08 +0000 | [diff] [blame] | 65 | const struct omap_sysinfo sysinfo = { |
Lokesh Vutla | 3c7dc01 | 2016-03-08 09:18:05 +0530 | [diff] [blame] | 66 | "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n" |
Lokesh Vutla | 40700ad | 2013-02-12 21:29:08 +0000 | [diff] [blame] | 67 | }; |
| 68 | |
Lokesh Vutla | 41963ee | 2016-03-08 09:18:06 +0530 | [diff] [blame] | 69 | static const struct emif_regs emif1_ddr3_532_mhz_1cs = { |
| 70 | .sdram_config_init = 0x61851ab2, |
| 71 | .sdram_config = 0x61851ab2, |
| 72 | .sdram_config2 = 0x08000000, |
| 73 | .ref_ctrl = 0x000040F1, |
| 74 | .ref_ctrl_final = 0x00001035, |
| 75 | .sdram_tim1 = 0xCCCF36B3, |
| 76 | .sdram_tim2 = 0x308F7FDA, |
| 77 | .sdram_tim3 = 0x427F88A8, |
| 78 | .read_idle_ctrl = 0x00050000, |
| 79 | .zq_config = 0x0007190B, |
| 80 | .temp_alert_config = 0x00000000, |
| 81 | .emif_ddr_phy_ctlr_1_init = 0x0024400B, |
| 82 | .emif_ddr_phy_ctlr_1 = 0x0E24400B, |
| 83 | .emif_ddr_ext_phy_ctrl_1 = 0x10040100, |
| 84 | .emif_ddr_ext_phy_ctrl_2 = 0x00910091, |
| 85 | .emif_ddr_ext_phy_ctrl_3 = 0x00950095, |
| 86 | .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, |
| 87 | .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, |
| 88 | .emif_rd_wr_lvl_rmp_win = 0x00000000, |
| 89 | .emif_rd_wr_lvl_rmp_ctl = 0x80000000, |
| 90 | .emif_rd_wr_lvl_ctl = 0x00000000, |
| 91 | .emif_rd_wr_exec_thresh = 0x00000305 |
| 92 | }; |
| 93 | |
| 94 | static const struct emif_regs emif2_ddr3_532_mhz_1cs = { |
| 95 | .sdram_config_init = 0x61851B32, |
| 96 | .sdram_config = 0x61851B32, |
| 97 | .sdram_config2 = 0x08000000, |
| 98 | .ref_ctrl = 0x000040F1, |
| 99 | .ref_ctrl_final = 0x00001035, |
| 100 | .sdram_tim1 = 0xCCCF36B3, |
| 101 | .sdram_tim2 = 0x308F7FDA, |
| 102 | .sdram_tim3 = 0x427F88A8, |
| 103 | .read_idle_ctrl = 0x00050000, |
| 104 | .zq_config = 0x0007190B, |
| 105 | .temp_alert_config = 0x00000000, |
| 106 | .emif_ddr_phy_ctlr_1_init = 0x0024400B, |
| 107 | .emif_ddr_phy_ctlr_1 = 0x0E24400B, |
| 108 | .emif_ddr_ext_phy_ctrl_1 = 0x10040100, |
| 109 | .emif_ddr_ext_phy_ctrl_2 = 0x00910091, |
| 110 | .emif_ddr_ext_phy_ctrl_3 = 0x00950095, |
| 111 | .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, |
| 112 | .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, |
| 113 | .emif_rd_wr_lvl_rmp_win = 0x00000000, |
| 114 | .emif_rd_wr_lvl_rmp_ctl = 0x80000000, |
| 115 | .emif_rd_wr_lvl_ctl = 0x00000000, |
| 116 | .emif_rd_wr_exec_thresh = 0x00000305 |
| 117 | }; |
| 118 | |
| 119 | static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { |
| 120 | .sdram_config_init = 0x61862B32, |
| 121 | .sdram_config = 0x61862B32, |
| 122 | .sdram_config2 = 0x08000000, |
| 123 | .ref_ctrl = 0x0000514C, |
| 124 | .ref_ctrl_final = 0x0000144A, |
| 125 | .sdram_tim1 = 0xD113781C, |
| 126 | .sdram_tim2 = 0x30717FE3, |
| 127 | .sdram_tim3 = 0x409F86A8, |
| 128 | .read_idle_ctrl = 0x00050000, |
| 129 | .zq_config = 0x5007190B, |
| 130 | .temp_alert_config = 0x00000000, |
| 131 | .emif_ddr_phy_ctlr_1_init = 0x0024400D, |
| 132 | .emif_ddr_phy_ctlr_1 = 0x0E24400D, |
| 133 | .emif_ddr_ext_phy_ctrl_1 = 0x10040100, |
| 134 | .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4, |
| 135 | .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9, |
| 136 | .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0, |
| 137 | .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0, |
| 138 | .emif_rd_wr_lvl_rmp_win = 0x00000000, |
| 139 | .emif_rd_wr_lvl_rmp_ctl = 0x80000000, |
| 140 | .emif_rd_wr_lvl_ctl = 0x00000000, |
| 141 | .emif_rd_wr_exec_thresh = 0x00000305 |
| 142 | }; |
| 143 | |
Ravi Babu | e103108 | 2016-03-15 18:09:14 -0500 | [diff] [blame] | 144 | const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = { |
| 145 | .sdram_config_init = 0x61862BB2, |
| 146 | .sdram_config = 0x61862BB2, |
| 147 | .sdram_config2 = 0x00000000, |
| 148 | .ref_ctrl = 0x0000514D, |
| 149 | .ref_ctrl_final = 0x0000144A, |
| 150 | .sdram_tim1 = 0xD1137824, |
| 151 | .sdram_tim2 = 0x30B37FE3, |
| 152 | .sdram_tim3 = 0x409F8AD8, |
| 153 | .read_idle_ctrl = 0x00050000, |
| 154 | .zq_config = 0x5007190B, |
| 155 | .temp_alert_config = 0x00000000, |
| 156 | .emif_ddr_phy_ctlr_1_init = 0x0824400E, |
| 157 | .emif_ddr_phy_ctlr_1 = 0x0E24400E, |
| 158 | .emif_ddr_ext_phy_ctrl_1 = 0x04040100, |
| 159 | .emif_ddr_ext_phy_ctrl_2 = 0x006B009F, |
| 160 | .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2, |
| 161 | .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8, |
| 162 | .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8, |
| 163 | .emif_rd_wr_lvl_rmp_win = 0x00000000, |
| 164 | .emif_rd_wr_lvl_rmp_ctl = 0x80000000, |
| 165 | .emif_rd_wr_lvl_ctl = 0x00000000, |
| 166 | .emif_rd_wr_exec_thresh = 0x00000305 |
| 167 | }; |
| 168 | |
Lokesh Vutla | b85fbcd | 2016-03-08 09:18:08 +0530 | [diff] [blame] | 169 | const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = { |
| 170 | .sdram_config_init = 0x61851ab2, |
| 171 | .sdram_config = 0x61851ab2, |
| 172 | .sdram_config2 = 0x08000000, |
| 173 | .ref_ctrl = 0x000040F1, |
| 174 | .ref_ctrl_final = 0x00001035, |
| 175 | .sdram_tim1 = 0xCCCF36B3, |
| 176 | .sdram_tim2 = 0x30BF7FDA, |
| 177 | .sdram_tim3 = 0x427F8BA8, |
| 178 | .read_idle_ctrl = 0x00050000, |
| 179 | .zq_config = 0x0007190B, |
| 180 | .temp_alert_config = 0x00000000, |
| 181 | .emif_ddr_phy_ctlr_1_init = 0x0024400B, |
| 182 | .emif_ddr_phy_ctlr_1 = 0x0E24400B, |
| 183 | .emif_ddr_ext_phy_ctrl_1 = 0x10040100, |
| 184 | .emif_ddr_ext_phy_ctrl_2 = 0x00910091, |
| 185 | .emif_ddr_ext_phy_ctrl_3 = 0x00950095, |
| 186 | .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, |
| 187 | .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, |
| 188 | .emif_rd_wr_lvl_rmp_win = 0x00000000, |
| 189 | .emif_rd_wr_lvl_rmp_ctl = 0x80000000, |
| 190 | .emif_rd_wr_lvl_ctl = 0x00000000, |
| 191 | .emif_rd_wr_exec_thresh = 0x00000305 |
| 192 | }; |
| 193 | |
| 194 | const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = { |
| 195 | .sdram_config_init = 0x61851B32, |
| 196 | .sdram_config = 0x61851B32, |
| 197 | .sdram_config2 = 0x08000000, |
| 198 | .ref_ctrl = 0x000040F1, |
| 199 | .ref_ctrl_final = 0x00001035, |
| 200 | .sdram_tim1 = 0xCCCF36B3, |
| 201 | .sdram_tim2 = 0x308F7FDA, |
| 202 | .sdram_tim3 = 0x427F88A8, |
| 203 | .read_idle_ctrl = 0x00050000, |
| 204 | .zq_config = 0x0007190B, |
| 205 | .temp_alert_config = 0x00000000, |
| 206 | .emif_ddr_phy_ctlr_1_init = 0x0024400B, |
| 207 | .emif_ddr_phy_ctlr_1 = 0x0E24400B, |
| 208 | .emif_ddr_ext_phy_ctrl_1 = 0x10040100, |
| 209 | .emif_ddr_ext_phy_ctrl_2 = 0x00910091, |
| 210 | .emif_ddr_ext_phy_ctrl_3 = 0x00950095, |
| 211 | .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, |
| 212 | .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, |
| 213 | .emif_rd_wr_lvl_rmp_win = 0x00000000, |
| 214 | .emif_rd_wr_lvl_rmp_ctl = 0x80000000, |
| 215 | .emif_rd_wr_lvl_ctl = 0x00000000, |
| 216 | .emif_rd_wr_exec_thresh = 0x00000305 |
| 217 | }; |
| 218 | |
Lokesh Vutla | 6f1038f | 2017-08-21 12:50:55 +0530 | [diff] [blame] | 219 | const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = { |
| 220 | .sdram_config_init = 0x61862B32, |
| 221 | .sdram_config = 0x61862B32, |
| 222 | .sdram_config2 = 0x00000000, |
| 223 | .ref_ctrl = 0x0000514C, |
| 224 | .ref_ctrl_final = 0x0000144A, |
| 225 | .sdram_tim1 = 0xD113783C, |
| 226 | .sdram_tim2 = 0x30B47FE3, |
| 227 | .sdram_tim3 = 0x409F8AD8, |
| 228 | .read_idle_ctrl = 0x00050000, |
| 229 | .zq_config = 0x5007190B, |
| 230 | .temp_alert_config = 0x00000000, |
| 231 | .emif_ddr_phy_ctlr_1_init = 0x0824400D, |
| 232 | .emif_ddr_phy_ctlr_1 = 0x0E24400D, |
| 233 | .emif_ddr_ext_phy_ctrl_1 = 0x04040100, |
| 234 | .emif_ddr_ext_phy_ctrl_2 = 0x006B009F, |
| 235 | .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2, |
| 236 | .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8, |
| 237 | .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8, |
| 238 | .emif_rd_wr_lvl_rmp_win = 0x00000000, |
| 239 | .emif_rd_wr_lvl_rmp_ctl = 0x80000000, |
| 240 | .emif_rd_wr_lvl_ctl = 0x00000000, |
| 241 | .emif_rd_wr_exec_thresh = 0x00000305 |
| 242 | }; |
| 243 | |
| 244 | const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = { |
| 245 | .sdram_config_init = 0x61862B32, |
| 246 | .sdram_config = 0x61862B32, |
| 247 | .sdram_config2 = 0x00000000, |
| 248 | .ref_ctrl = 0x0000514C, |
| 249 | .ref_ctrl_final = 0x0000144A, |
| 250 | .sdram_tim1 = 0xD113781C, |
| 251 | .sdram_tim2 = 0x30B47FE3, |
| 252 | .sdram_tim3 = 0x409F8AD8, |
| 253 | .read_idle_ctrl = 0x00050000, |
| 254 | .zq_config = 0x5007190B, |
| 255 | .temp_alert_config = 0x00000000, |
| 256 | .emif_ddr_phy_ctlr_1_init = 0x0824400D, |
| 257 | .emif_ddr_phy_ctlr_1 = 0x0E24400D, |
| 258 | .emif_ddr_ext_phy_ctrl_1 = 0x04040100, |
| 259 | .emif_ddr_ext_phy_ctrl_2 = 0x006B009F, |
| 260 | .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2, |
| 261 | .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8, |
| 262 | .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8, |
| 263 | .emif_rd_wr_lvl_rmp_win = 0x00000000, |
| 264 | .emif_rd_wr_lvl_rmp_ctl = 0x80000000, |
| 265 | .emif_rd_wr_lvl_ctl = 0x00000000, |
| 266 | .emif_rd_wr_exec_thresh = 0x00000305 |
| 267 | }; |
| 268 | |
Lokesh Vutla | 41963ee | 2016-03-08 09:18:06 +0530 | [diff] [blame] | 269 | void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) |
| 270 | { |
Lokesh Vutla | b85fbcd | 2016-03-08 09:18:08 +0530 | [diff] [blame] | 271 | u64 ram_size; |
| 272 | |
| 273 | ram_size = board_ti_get_emif_size(); |
| 274 | |
Lokesh Vutla | 41963ee | 2016-03-08 09:18:06 +0530 | [diff] [blame] | 275 | switch (omap_revision()) { |
| 276 | case DRA752_ES1_0: |
| 277 | case DRA752_ES1_1: |
| 278 | case DRA752_ES2_0: |
| 279 | switch (emif_nr) { |
| 280 | case 1: |
Lokesh Vutla | b85fbcd | 2016-03-08 09:18:08 +0530 | [diff] [blame] | 281 | if (ram_size > CONFIG_MAX_MEM_MAPPED) |
| 282 | *regs = &emif1_ddr3_532_mhz_1cs_2G; |
| 283 | else |
| 284 | *regs = &emif1_ddr3_532_mhz_1cs; |
Lokesh Vutla | 41963ee | 2016-03-08 09:18:06 +0530 | [diff] [blame] | 285 | break; |
| 286 | case 2: |
Lokesh Vutla | b85fbcd | 2016-03-08 09:18:08 +0530 | [diff] [blame] | 287 | if (ram_size > CONFIG_MAX_MEM_MAPPED) |
| 288 | *regs = &emif2_ddr3_532_mhz_1cs_2G; |
| 289 | else |
| 290 | *regs = &emif2_ddr3_532_mhz_1cs; |
Lokesh Vutla | 41963ee | 2016-03-08 09:18:06 +0530 | [diff] [blame] | 291 | break; |
| 292 | } |
| 293 | break; |
Lokesh Vutla | 69483e6 | 2017-12-29 11:47:51 +0530 | [diff] [blame] | 294 | case DRA762_ABZ_ES1_0: |
| 295 | case DRA762_ACD_ES1_0: |
Lokesh Vutla | 6f1038f | 2017-08-21 12:50:55 +0530 | [diff] [blame] | 296 | case DRA762_ES1_0: |
| 297 | if (emif_nr == 1) |
| 298 | *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76; |
| 299 | else |
| 300 | *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76; |
| 301 | break; |
Lokesh Vutla | 41963ee | 2016-03-08 09:18:06 +0530 | [diff] [blame] | 302 | case DRA722_ES1_0: |
Ravi Babu | e103108 | 2016-03-15 18:09:14 -0500 | [diff] [blame] | 303 | case DRA722_ES2_0: |
Vishal Mahaveer | 42d25eb | 2017-08-26 16:51:22 -0500 | [diff] [blame] | 304 | case DRA722_ES2_1: |
Ravi Babu | e103108 | 2016-03-15 18:09:14 -0500 | [diff] [blame] | 305 | if (ram_size < CONFIG_MAX_MEM_MAPPED) |
| 306 | *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; |
| 307 | else |
| 308 | *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2; |
Lokesh Vutla | 41963ee | 2016-03-08 09:18:06 +0530 | [diff] [blame] | 309 | break; |
| 310 | default: |
| 311 | *regs = &emif1_ddr3_532_mhz_1cs; |
| 312 | } |
| 313 | } |
| 314 | |
| 315 | static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = { |
| 316 | .dmm_lisa_map_0 = 0x0, |
| 317 | .dmm_lisa_map_1 = 0x80640300, |
| 318 | .dmm_lisa_map_2 = 0xC0500220, |
| 319 | .dmm_lisa_map_3 = 0xFF020100, |
| 320 | .is_ma_present = 0x1 |
| 321 | }; |
| 322 | |
| 323 | static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = { |
| 324 | .dmm_lisa_map_0 = 0x0, |
| 325 | .dmm_lisa_map_1 = 0x0, |
| 326 | .dmm_lisa_map_2 = 0x80600100, |
| 327 | .dmm_lisa_map_3 = 0xFF020100, |
| 328 | .is_ma_present = 0x1 |
| 329 | }; |
| 330 | |
Lokesh Vutla | b85fbcd | 2016-03-08 09:18:08 +0530 | [diff] [blame] | 331 | const struct dmm_lisa_map_regs lisa_map_dra7_2GB = { |
| 332 | .dmm_lisa_map_0 = 0x0, |
| 333 | .dmm_lisa_map_1 = 0x0, |
| 334 | .dmm_lisa_map_2 = 0x80740300, |
| 335 | .dmm_lisa_map_3 = 0xFF020100, |
| 336 | .is_ma_present = 0x1 |
| 337 | }; |
| 338 | |
Ravi Babu | e103108 | 2016-03-15 18:09:14 -0500 | [diff] [blame] | 339 | /* |
| 340 | * DRA722 EVM EMIF1 2GB CONFIGURATION |
| 341 | * EMIF1 4 devices of 512Mb x 8 Micron |
| 342 | */ |
| 343 | const struct dmm_lisa_map_regs lisa_map_2G_x_4 = { |
| 344 | .dmm_lisa_map_0 = 0x0, |
| 345 | .dmm_lisa_map_1 = 0x0, |
| 346 | .dmm_lisa_map_2 = 0x80700100, |
| 347 | .dmm_lisa_map_3 = 0xFF020100, |
| 348 | .is_ma_present = 0x1 |
| 349 | }; |
| 350 | |
Lokesh Vutla | 41963ee | 2016-03-08 09:18:06 +0530 | [diff] [blame] | 351 | void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) |
| 352 | { |
Lokesh Vutla | b85fbcd | 2016-03-08 09:18:08 +0530 | [diff] [blame] | 353 | u64 ram_size; |
| 354 | |
| 355 | ram_size = board_ti_get_emif_size(); |
| 356 | |
Lokesh Vutla | 41963ee | 2016-03-08 09:18:06 +0530 | [diff] [blame] | 357 | switch (omap_revision()) { |
Lokesh Vutla | 69483e6 | 2017-12-29 11:47:51 +0530 | [diff] [blame] | 358 | case DRA762_ABZ_ES1_0: |
| 359 | case DRA762_ACD_ES1_0: |
Lokesh Vutla | 6f1038f | 2017-08-21 12:50:55 +0530 | [diff] [blame] | 360 | case DRA762_ES1_0: |
Lokesh Vutla | 41963ee | 2016-03-08 09:18:06 +0530 | [diff] [blame] | 361 | case DRA752_ES1_0: |
| 362 | case DRA752_ES1_1: |
| 363 | case DRA752_ES2_0: |
Lokesh Vutla | b85fbcd | 2016-03-08 09:18:08 +0530 | [diff] [blame] | 364 | if (ram_size > CONFIG_MAX_MEM_MAPPED) |
| 365 | *dmm_lisa_regs = &lisa_map_dra7_2GB; |
| 366 | else |
| 367 | *dmm_lisa_regs = &lisa_map_dra7_1536MB; |
Lokesh Vutla | 41963ee | 2016-03-08 09:18:06 +0530 | [diff] [blame] | 368 | break; |
| 369 | case DRA722_ES1_0: |
Ravi Babu | e103108 | 2016-03-15 18:09:14 -0500 | [diff] [blame] | 370 | case DRA722_ES2_0: |
Vishal Mahaveer | 42d25eb | 2017-08-26 16:51:22 -0500 | [diff] [blame] | 371 | case DRA722_ES2_1: |
Lokesh Vutla | 41963ee | 2016-03-08 09:18:06 +0530 | [diff] [blame] | 372 | default: |
Ravi Babu | e103108 | 2016-03-15 18:09:14 -0500 | [diff] [blame] | 373 | if (ram_size < CONFIG_MAX_MEM_MAPPED) |
| 374 | *dmm_lisa_regs = &lisa_map_2G_x_2; |
| 375 | else |
| 376 | *dmm_lisa_regs = &lisa_map_2G_x_4; |
| 377 | break; |
Lokesh Vutla | 41963ee | 2016-03-08 09:18:06 +0530 | [diff] [blame] | 378 | } |
| 379 | } |
| 380 | |
Keerthy | c805623 | 2016-06-07 16:05:25 +0530 | [diff] [blame] | 381 | struct vcores_data dra752_volts = { |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 382 | .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, |
| 383 | .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, |
Keerthy | c805623 | 2016-06-07 16:05:25 +0530 | [diff] [blame] | 384 | .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
| 385 | .mpu.addr = TPS659038_REG_ADDR_SMPS12, |
| 386 | .mpu.pmic = &tps659038, |
| 387 | .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, |
| 388 | |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 389 | .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, |
| 390 | .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, |
| 391 | .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, |
| 392 | .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, |
| 393 | .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, |
| 394 | .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, |
Keerthy | c805623 | 2016-06-07 16:05:25 +0530 | [diff] [blame] | 395 | .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
| 396 | .eve.addr = TPS659038_REG_ADDR_SMPS45, |
| 397 | .eve.pmic = &tps659038, |
| 398 | .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, |
| 399 | |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 400 | .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, |
| 401 | .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, |
| 402 | .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, |
| 403 | .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, |
| 404 | .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, |
| 405 | .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, |
Keerthy | c805623 | 2016-06-07 16:05:25 +0530 | [diff] [blame] | 406 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
| 407 | .gpu.addr = TPS659038_REG_ADDR_SMPS6, |
| 408 | .gpu.pmic = &tps659038, |
| 409 | .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, |
| 410 | |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 411 | .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, |
| 412 | .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, |
Keerthy | c805623 | 2016-06-07 16:05:25 +0530 | [diff] [blame] | 413 | .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
| 414 | .core.addr = TPS659038_REG_ADDR_SMPS7, |
| 415 | .core.pmic = &tps659038, |
| 416 | |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 417 | .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, |
| 418 | .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, |
| 419 | .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, |
| 420 | .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, |
| 421 | .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, |
| 422 | .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, |
Keerthy | c805623 | 2016-06-07 16:05:25 +0530 | [diff] [blame] | 423 | .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
| 424 | .iva.addr = TPS659038_REG_ADDR_SMPS8, |
| 425 | .iva.pmic = &tps659038, |
| 426 | .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, |
| 427 | }; |
| 428 | |
Keerthy | 1b21f55 | 2017-08-21 12:50:54 +0530 | [diff] [blame] | 429 | struct vcores_data dra76x_volts = { |
| 430 | .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, |
| 431 | .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, |
| 432 | .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
| 433 | .mpu.addr = LP87565_REG_ADDR_BUCK01, |
| 434 | .mpu.pmic = &lp87565, |
| 435 | .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, |
| 436 | |
| 437 | .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, |
| 438 | .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, |
| 439 | .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, |
| 440 | .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, |
| 441 | .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, |
| 442 | .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, |
| 443 | .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
| 444 | .eve.addr = TPS65917_REG_ADDR_SMPS1, |
| 445 | .eve.pmic = &tps659038, |
| 446 | .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, |
| 447 | |
| 448 | .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, |
| 449 | .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, |
| 450 | .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, |
| 451 | .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, |
| 452 | .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, |
| 453 | .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, |
| 454 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
| 455 | .gpu.addr = LP87565_REG_ADDR_BUCK23, |
| 456 | .gpu.pmic = &lp87565, |
| 457 | .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, |
| 458 | |
| 459 | .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, |
| 460 | .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, |
| 461 | .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
| 462 | .core.addr = TPS65917_REG_ADDR_SMPS3, |
| 463 | .core.pmic = &tps659038, |
| 464 | |
| 465 | .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, |
| 466 | .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, |
| 467 | .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, |
| 468 | .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, |
| 469 | .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, |
| 470 | .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, |
| 471 | .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
| 472 | .iva.addr = TPS65917_REG_ADDR_SMPS4, |
| 473 | .iva.pmic = &tps659038, |
| 474 | .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, |
| 475 | }; |
| 476 | |
Keerthy | c805623 | 2016-06-07 16:05:25 +0530 | [diff] [blame] | 477 | struct vcores_data dra722_volts = { |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 478 | .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, |
| 479 | .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, |
Keerthy | c805623 | 2016-06-07 16:05:25 +0530 | [diff] [blame] | 480 | .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
| 481 | .mpu.addr = TPS65917_REG_ADDR_SMPS1, |
| 482 | .mpu.pmic = &tps659038, |
| 483 | .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, |
| 484 | |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 485 | .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, |
| 486 | .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, |
Keerthy | c805623 | 2016-06-07 16:05:25 +0530 | [diff] [blame] | 487 | .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
| 488 | .core.addr = TPS65917_REG_ADDR_SMPS2, |
| 489 | .core.pmic = &tps659038, |
| 490 | |
| 491 | /* |
| 492 | * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x |
| 493 | * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM. |
| 494 | */ |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 495 | .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, |
| 496 | .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, |
| 497 | .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, |
| 498 | .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, |
| 499 | .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, |
| 500 | .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, |
Keerthy | c805623 | 2016-06-07 16:05:25 +0530 | [diff] [blame] | 501 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
| 502 | .gpu.addr = TPS65917_REG_ADDR_SMPS3, |
| 503 | .gpu.pmic = &tps659038, |
| 504 | .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, |
| 505 | |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 506 | .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, |
| 507 | .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, |
| 508 | .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, |
| 509 | .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, |
| 510 | .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, |
| 511 | .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, |
Keerthy | c805623 | 2016-06-07 16:05:25 +0530 | [diff] [blame] | 512 | .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
| 513 | .eve.addr = TPS65917_REG_ADDR_SMPS3, |
| 514 | .eve.pmic = &tps659038, |
| 515 | .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, |
| 516 | |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 517 | .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, |
| 518 | .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, |
| 519 | .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, |
| 520 | .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, |
| 521 | .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, |
| 522 | .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, |
Keerthy | c805623 | 2016-06-07 16:05:25 +0530 | [diff] [blame] | 523 | .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
| 524 | .iva.addr = TPS65917_REG_ADDR_SMPS3, |
| 525 | .iva.pmic = &tps659038, |
| 526 | .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, |
| 527 | }; |
| 528 | |
Keerthy | 4d4e34b | 2016-11-23 13:25:27 +0530 | [diff] [blame] | 529 | struct vcores_data dra718_volts = { |
| 530 | /* |
| 531 | * In the case of dra71x GPU MPU and CORE |
| 532 | * are all powered up by BUCK0 of LP873X PMIC |
| 533 | */ |
| 534 | .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, |
| 535 | .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, |
| 536 | .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
| 537 | .mpu.addr = LP873X_REG_ADDR_BUCK0, |
| 538 | .mpu.pmic = &lp8733, |
| 539 | .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, |
| 540 | |
| 541 | .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, |
| 542 | .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, |
| 543 | .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
| 544 | .core.addr = LP873X_REG_ADDR_BUCK0, |
| 545 | .core.pmic = &lp8733, |
| 546 | |
| 547 | .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, |
| 548 | .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, |
| 549 | .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
| 550 | .gpu.addr = LP873X_REG_ADDR_BUCK0, |
| 551 | .gpu.pmic = &lp8733, |
| 552 | .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, |
| 553 | |
| 554 | /* |
| 555 | * The DSPEVE and IVA rails are grouped on DRA71x-evm |
| 556 | * and are powered by BUCK1 of LP873X PMIC |
| 557 | */ |
| 558 | .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, |
Lokesh Vutla | cae8428 | 2017-04-20 14:07:52 +0530 | [diff] [blame] | 559 | .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, |
Keerthy | 4d4e34b | 2016-11-23 13:25:27 +0530 | [diff] [blame] | 560 | .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, |
Lokesh Vutla | cae8428 | 2017-04-20 14:07:52 +0530 | [diff] [blame] | 561 | .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, |
Keerthy | 4d4e34b | 2016-11-23 13:25:27 +0530 | [diff] [blame] | 562 | .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
| 563 | .eve.addr = LP873X_REG_ADDR_BUCK1, |
| 564 | .eve.pmic = &lp8733, |
| 565 | .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, |
| 566 | |
| 567 | .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, |
Lokesh Vutla | cae8428 | 2017-04-20 14:07:52 +0530 | [diff] [blame] | 568 | .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, |
Keerthy | 4d4e34b | 2016-11-23 13:25:27 +0530 | [diff] [blame] | 569 | .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, |
Lokesh Vutla | cae8428 | 2017-04-20 14:07:52 +0530 | [diff] [blame] | 570 | .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, |
Keerthy | 4d4e34b | 2016-11-23 13:25:27 +0530 | [diff] [blame] | 571 | .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, |
| 572 | .iva.addr = LP873X_REG_ADDR_BUCK1, |
| 573 | .iva.pmic = &lp8733, |
| 574 | .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, |
| 575 | }; |
| 576 | |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 577 | int get_voltrail_opp(int rail_offset) |
| 578 | { |
| 579 | int opp; |
| 580 | |
| 581 | switch (rail_offset) { |
| 582 | case VOLT_MPU: |
| 583 | opp = DRA7_MPU_OPP; |
Lokesh Vutla | cae8428 | 2017-04-20 14:07:52 +0530 | [diff] [blame] | 584 | /* DRA71x supports only OPP_NOM for MPU */ |
| 585 | if (board_is_dra71x_evm()) |
| 586 | opp = OPP_NOM; |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 587 | break; |
| 588 | case VOLT_CORE: |
| 589 | opp = DRA7_CORE_OPP; |
Lokesh Vutla | cae8428 | 2017-04-20 14:07:52 +0530 | [diff] [blame] | 590 | /* DRA71x supports only OPP_NOM for CORE */ |
| 591 | if (board_is_dra71x_evm()) |
| 592 | opp = OPP_NOM; |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 593 | break; |
| 594 | case VOLT_GPU: |
| 595 | opp = DRA7_GPU_OPP; |
Lokesh Vutla | cae8428 | 2017-04-20 14:07:52 +0530 | [diff] [blame] | 596 | /* DRA71x supports only OPP_NOM for GPU */ |
| 597 | if (board_is_dra71x_evm()) |
| 598 | opp = OPP_NOM; |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 599 | break; |
| 600 | case VOLT_EVE: |
| 601 | opp = DRA7_DSPEVE_OPP; |
Lokesh Vutla | cae8428 | 2017-04-20 14:07:52 +0530 | [diff] [blame] | 602 | /* |
| 603 | * DRA71x does not support OPP_OD for EVE. |
| 604 | * If OPP_OD is selected by menuconfig, fallback |
| 605 | * to OPP_NOM. |
| 606 | */ |
| 607 | if (board_is_dra71x_evm() && opp == OPP_OD) |
| 608 | opp = OPP_NOM; |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 609 | break; |
| 610 | case VOLT_IVA: |
| 611 | opp = DRA7_IVA_OPP; |
Lokesh Vutla | cae8428 | 2017-04-20 14:07:52 +0530 | [diff] [blame] | 612 | /* |
| 613 | * DRA71x does not support OPP_OD for IVA. |
| 614 | * If OPP_OD is selected by menuconfig, fallback |
| 615 | * to OPP_NOM. |
| 616 | */ |
| 617 | if (board_is_dra71x_evm() && opp == OPP_OD) |
| 618 | opp = OPP_NOM; |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 619 | break; |
| 620 | default: |
| 621 | opp = OPP_NOM; |
| 622 | } |
| 623 | |
| 624 | return opp; |
| 625 | } |
| 626 | |
Lokesh Vutla | 40700ad | 2013-02-12 21:29:08 +0000 | [diff] [blame] | 627 | /** |
| 628 | * @brief board_init |
| 629 | * |
| 630 | * @return 0 |
| 631 | */ |
| 632 | int board_init(void) |
| 633 | { |
| 634 | gpmc_init(); |
| 635 | gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ |
| 636 | |
| 637 | return 0; |
| 638 | } |
| 639 | |
Simon Glass | 2f949c3 | 2017-03-31 08:40:32 -0600 | [diff] [blame] | 640 | int dram_init_banksize(void) |
Lokesh Vutla | 0deb333 | 2016-03-08 09:18:09 +0530 | [diff] [blame] | 641 | { |
| 642 | u64 ram_size; |
| 643 | |
| 644 | ram_size = board_ti_get_emif_size(); |
| 645 | |
| 646 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; |
| 647 | gd->bd->bi_dram[0].size = get_effective_memsize(); |
| 648 | if (ram_size > CONFIG_MAX_MEM_MAPPED) { |
| 649 | gd->bd->bi_dram[1].start = 0x200000000; |
| 650 | gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED; |
| 651 | } |
Simon Glass | 2f949c3 | 2017-03-31 08:40:32 -0600 | [diff] [blame] | 652 | |
| 653 | return 0; |
Lokesh Vutla | 0deb333 | 2016-03-08 09:18:09 +0530 | [diff] [blame] | 654 | } |
| 655 | |
Jean-Jacques Hiblot | a58fe0a | 2018-11-29 10:57:41 +0100 | [diff] [blame] | 656 | #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL) |
| 657 | static int device_okay(const char *path) |
| 658 | { |
| 659 | int node; |
| 660 | |
| 661 | node = fdt_path_offset(gd->fdt_blob, path); |
| 662 | if (node < 0) |
| 663 | return 0; |
| 664 | |
| 665 | return fdtdec_get_is_enabled(gd->fdt_blob, node); |
| 666 | } |
| 667 | #endif |
| 668 | |
Roger Quadros | f019ee8 | 2013-11-11 16:56:44 +0200 | [diff] [blame] | 669 | int board_late_init(void) |
| 670 | { |
Lokesh Vutla | 6d576a7 | 2014-07-14 19:57:58 +0530 | [diff] [blame] | 671 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
Lokesh Vutla | 3c7dc01 | 2016-03-08 09:18:05 +0530 | [diff] [blame] | 672 | char *name = "unknown"; |
| 673 | |
Lokesh Vutla | 9e23ab5 | 2016-06-29 14:50:41 +0530 | [diff] [blame] | 674 | if (is_dra72x()) { |
| 675 | if (board_is_dra72x_revc_or_later()) |
| 676 | name = "dra72x-revc"; |
Lokesh Vutla | b9d8f8e | 2016-11-23 13:25:24 +0530 | [diff] [blame] | 677 | else if (board_is_dra71x_evm()) |
| 678 | name = "dra71x"; |
Lokesh Vutla | 9e23ab5 | 2016-06-29 14:50:41 +0530 | [diff] [blame] | 679 | else |
| 680 | name = "dra72x"; |
Lokesh Vutla | 69483e6 | 2017-12-29 11:47:51 +0530 | [diff] [blame] | 681 | } else if (is_dra76x_abz()) { |
| 682 | name = "dra76x_abz"; |
| 683 | } else if (is_dra76x_acd()) { |
| 684 | name = "dra76x_acd"; |
Lokesh Vutla | 9e23ab5 | 2016-06-29 14:50:41 +0530 | [diff] [blame] | 685 | } else { |
Lokesh Vutla | 3c7dc01 | 2016-03-08 09:18:05 +0530 | [diff] [blame] | 686 | name = "dra7xx"; |
Lokesh Vutla | 9e23ab5 | 2016-06-29 14:50:41 +0530 | [diff] [blame] | 687 | } |
Lokesh Vutla | 3c7dc01 | 2016-03-08 09:18:05 +0530 | [diff] [blame] | 688 | |
| 689 | set_board_info_env(name); |
Dileep Katta | 7354dfc | 2015-03-25 04:04:51 +0530 | [diff] [blame] | 690 | |
Lokesh Vutla | 73368b7 | 2016-11-29 11:58:01 +0530 | [diff] [blame] | 691 | /* |
| 692 | * Default FIT boot on HS devices. Non FIT images are not allowed |
| 693 | * on HS devices. |
| 694 | */ |
| 695 | if (get_device_type() == HS_DEVICE) |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 696 | env_set("boot_fit", "1"); |
Lokesh Vutla | 73368b7 | 2016-11-29 11:58:01 +0530 | [diff] [blame] | 697 | |
Paul Kocialkowski | 2edadee | 2015-08-27 19:37:12 +0200 | [diff] [blame] | 698 | omap_die_id_serial(); |
Semen Protsenko | 4a84532 | 2017-05-22 19:16:42 +0300 | [diff] [blame] | 699 | omap_set_fastboot_vars(); |
Keerthy | be0c1f1 | 2017-10-12 10:18:45 +0530 | [diff] [blame] | 700 | |
| 701 | /* |
| 702 | * Hook the LDO1 regulator to EN pin. This applies only to LP8733 |
| 703 | * Rest all regulators are hooked to EN Pin at reset. |
| 704 | */ |
| 705 | if (board_is_dra71x_evm()) |
| 706 | palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7); |
Lokesh Vutla | 6d576a7 | 2014-07-14 19:57:58 +0530 | [diff] [blame] | 707 | #endif |
Jean-Jacques Hiblot | a58fe0a | 2018-11-29 10:57:41 +0100 | [diff] [blame] | 708 | #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL) |
| 709 | if (device_okay("/ocp/omap_dwc3_1@48880000")) |
| 710 | enable_usb_clocks(0); |
| 711 | if (device_okay("/ocp/omap_dwc3_2@488c0000")) |
| 712 | enable_usb_clocks(1); |
| 713 | #endif |
Roger Quadros | f019ee8 | 2013-11-11 16:56:44 +0200 | [diff] [blame] | 714 | return 0; |
| 715 | } |
Lokesh Vutla | 3c7dc01 | 2016-03-08 09:18:05 +0530 | [diff] [blame] | 716 | |
| 717 | #ifdef CONFIG_SPL_BUILD |
| 718 | void do_board_detect(void) |
| 719 | { |
| 720 | int rc; |
| 721 | |
| 722 | rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS, |
| 723 | CONFIG_EEPROM_CHIP_ADDRESS); |
| 724 | if (rc) |
| 725 | printf("ti_i2c_eeprom_init failed %d\n", rc); |
| 726 | } |
| 727 | |
| 728 | #else |
| 729 | |
| 730 | void do_board_detect(void) |
| 731 | { |
| 732 | char *bname = NULL; |
| 733 | int rc; |
| 734 | |
| 735 | rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS, |
| 736 | CONFIG_EEPROM_CHIP_ADDRESS); |
| 737 | if (rc) |
| 738 | printf("ti_i2c_eeprom_init failed %d\n", rc); |
| 739 | |
| 740 | if (board_is_dra74x_evm()) { |
| 741 | bname = "DRA74x EVM"; |
Ravi Babu | e103108 | 2016-03-15 18:09:14 -0500 | [diff] [blame] | 742 | } else if (board_is_dra72x_evm()) { |
| 743 | bname = "DRA72x EVM"; |
Lokesh Vutla | b9d8f8e | 2016-11-23 13:25:24 +0530 | [diff] [blame] | 744 | } else if (board_is_dra71x_evm()) { |
| 745 | bname = "DRA71x EVM"; |
Lokesh Vutla | 1337613 | 2017-08-21 12:50:53 +0530 | [diff] [blame] | 746 | } else if (board_is_dra76x_evm()) { |
| 747 | bname = "DRA76x EVM"; |
Lokesh Vutla | 3c7dc01 | 2016-03-08 09:18:05 +0530 | [diff] [blame] | 748 | } else { |
Ravi Babu | e103108 | 2016-03-15 18:09:14 -0500 | [diff] [blame] | 749 | /* If EEPROM is not populated */ |
Lokesh Vutla | 3c7dc01 | 2016-03-08 09:18:05 +0530 | [diff] [blame] | 750 | if (is_dra72x()) |
| 751 | bname = "DRA72x EVM"; |
| 752 | else |
| 753 | bname = "DRA74x EVM"; |
| 754 | } |
| 755 | |
| 756 | if (bname) |
| 757 | snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN, |
| 758 | "Board: %s REV %s\n", bname, board_ti_get_rev()); |
| 759 | } |
| 760 | #endif /* CONFIG_SPL_BUILD */ |
Roger Quadros | f019ee8 | 2013-11-11 16:56:44 +0200 | [diff] [blame] | 761 | |
Keerthy | c805623 | 2016-06-07 16:05:25 +0530 | [diff] [blame] | 762 | void vcores_init(void) |
| 763 | { |
| 764 | if (board_is_dra74x_evm()) { |
| 765 | *omap_vcores = &dra752_volts; |
| 766 | } else if (board_is_dra72x_evm()) { |
| 767 | *omap_vcores = &dra722_volts; |
Keerthy | 4d4e34b | 2016-11-23 13:25:27 +0530 | [diff] [blame] | 768 | } else if (board_is_dra71x_evm()) { |
| 769 | *omap_vcores = &dra718_volts; |
Keerthy | 1b21f55 | 2017-08-21 12:50:54 +0530 | [diff] [blame] | 770 | } else if (board_is_dra76x_evm()) { |
| 771 | *omap_vcores = &dra76x_volts; |
Keerthy | c805623 | 2016-06-07 16:05:25 +0530 | [diff] [blame] | 772 | } else { |
| 773 | /* If EEPROM is not populated */ |
| 774 | if (is_dra72x()) |
| 775 | *omap_vcores = &dra722_volts; |
| 776 | else |
| 777 | *omap_vcores = &dra752_volts; |
| 778 | } |
| 779 | } |
| 780 | |
Paul Kocialkowski | a00b1e5 | 2016-02-27 19:18:56 +0100 | [diff] [blame] | 781 | void set_muxconf_regs(void) |
Lokesh Vutla | 40700ad | 2013-02-12 21:29:08 +0000 | [diff] [blame] | 782 | { |
| 783 | do_set_mux32((*ctrl)->control_padconf_core_base, |
Lokesh Vutla | 1fd8022 | 2015-06-04 16:42:38 +0530 | [diff] [blame] | 784 | early_padconf, ARRAY_SIZE(early_padconf)); |
Lokesh Vutla | 40700ad | 2013-02-12 21:29:08 +0000 | [diff] [blame] | 785 | } |
Franklin S Cooper Jr | 236fca8 | 2019-02-27 13:29:36 +0530 | [diff] [blame] | 786 | |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 787 | #if defined(CONFIG_MTD_RAW_NAND) |
Franklin S Cooper Jr | 236fca8 | 2019-02-27 13:29:36 +0530 | [diff] [blame] | 788 | static int nand_sw_detect(void) |
| 789 | { |
| 790 | int rc; |
| 791 | uchar data[2]; |
| 792 | struct udevice *dev; |
| 793 | |
| 794 | rc = i2c_get_chip_for_busnum(NAND_PCF8575_I2C_BUS_NUM, |
| 795 | NAND_PCF8575_ADDR, 0, &dev); |
| 796 | if (rc) |
| 797 | return -1; |
| 798 | |
| 799 | rc = dm_i2c_read(dev, 0, (uint8_t *)&data, sizeof(data)); |
| 800 | if (rc) |
| 801 | return -1; |
| 802 | |
| 803 | /* We are only interested in P10 and P11 on PCF8575 which is equal to |
| 804 | * bits 8 and 9. |
| 805 | */ |
| 806 | data[1] = data[1] & 0x3; |
| 807 | |
| 808 | /* Ensure only P11 is set and P10 is cleared. This ensures only |
| 809 | * NAND (P10) is configured and not NOR (P11) which are both low |
| 810 | * true signals. NAND and NOR settings should not be enabled at |
| 811 | * the same time. |
| 812 | */ |
| 813 | if (data[1] == 0x2) |
| 814 | return 0; |
| 815 | |
| 816 | return -1; |
| 817 | } |
| 818 | #else |
| 819 | int nand_sw_detect(void) |
| 820 | { |
| 821 | return -1; |
| 822 | } |
| 823 | #endif |
Lokesh Vutla | 40700ad | 2013-02-12 21:29:08 +0000 | [diff] [blame] | 824 | |
Lokesh Vutla | 1fd8022 | 2015-06-04 16:42:38 +0530 | [diff] [blame] | 825 | #ifdef CONFIG_IODELAY_RECALIBRATION |
| 826 | void recalibrate_iodelay(void) |
| 827 | { |
Nishanth Menon | d3b7d85 | 2016-03-15 18:09:17 -0500 | [diff] [blame] | 828 | struct pad_conf_entry const *pads, *delta_pads = NULL; |
Nishanth Menon | 6759e7f | 2015-08-13 09:50:59 -0500 | [diff] [blame] | 829 | struct iodelay_cfg_entry const *iodelay; |
Nishanth Menon | d3b7d85 | 2016-03-15 18:09:17 -0500 | [diff] [blame] | 830 | int npads, niodelays, delta_npads = 0; |
| 831 | int ret; |
Nishanth Menon | 6759e7f | 2015-08-13 09:50:59 -0500 | [diff] [blame] | 832 | |
| 833 | switch (omap_revision()) { |
| 834 | case DRA722_ES1_0: |
Nishanth Menon | d3b7d85 | 2016-03-15 18:09:17 -0500 | [diff] [blame] | 835 | case DRA722_ES2_0: |
Vishal Mahaveer | 42d25eb | 2017-08-26 16:51:22 -0500 | [diff] [blame] | 836 | case DRA722_ES2_1: |
Nishanth Menon | d3b7d85 | 2016-03-15 18:09:17 -0500 | [diff] [blame] | 837 | pads = dra72x_core_padconf_array_common; |
| 838 | npads = ARRAY_SIZE(dra72x_core_padconf_array_common); |
Lokesh Vutla | 52ac1fe | 2016-11-23 13:25:25 +0530 | [diff] [blame] | 839 | if (board_is_dra71x_evm()) { |
| 840 | pads = dra71x_core_padconf_array; |
| 841 | npads = ARRAY_SIZE(dra71x_core_padconf_array); |
| 842 | iodelay = dra71_iodelay_cfg_array; |
| 843 | niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array); |
Franklin S Cooper Jr | 236fca8 | 2019-02-27 13:29:36 +0530 | [diff] [blame] | 844 | /* If SW8 on the EVM is set to enable NAND then |
| 845 | * overwrite the pins used by VOUT3 with NAND. |
| 846 | */ |
| 847 | if (!nand_sw_detect()) { |
| 848 | delta_pads = dra71x_nand_padconf_array; |
| 849 | delta_npads = |
| 850 | ARRAY_SIZE(dra71x_nand_padconf_array); |
| 851 | } else { |
| 852 | delta_pads = dra71x_vout3_padconf_array; |
| 853 | delta_npads = |
| 854 | ARRAY_SIZE(dra71x_vout3_padconf_array); |
| 855 | } |
| 856 | |
Lokesh Vutla | 52ac1fe | 2016-11-23 13:25:25 +0530 | [diff] [blame] | 857 | } else if (board_is_dra72x_revc_or_later()) { |
Nishanth Menon | d3b7d85 | 2016-03-15 18:09:17 -0500 | [diff] [blame] | 858 | delta_pads = dra72x_rgmii_padconf_array_revc; |
| 859 | delta_npads = |
| 860 | ARRAY_SIZE(dra72x_rgmii_padconf_array_revc); |
| 861 | iodelay = dra72_iodelay_cfg_array_revc; |
| 862 | niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc); |
| 863 | } else { |
| 864 | delta_pads = dra72x_rgmii_padconf_array_revb; |
| 865 | delta_npads = |
| 866 | ARRAY_SIZE(dra72x_rgmii_padconf_array_revb); |
| 867 | iodelay = dra72_iodelay_cfg_array_revb; |
| 868 | niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb); |
| 869 | } |
Nishanth Menon | 6759e7f | 2015-08-13 09:50:59 -0500 | [diff] [blame] | 870 | break; |
| 871 | case DRA752_ES1_0: |
| 872 | case DRA752_ES1_1: |
| 873 | pads = dra74x_core_padconf_array; |
| 874 | npads = ARRAY_SIZE(dra74x_core_padconf_array); |
| 875 | iodelay = dra742_es1_1_iodelay_cfg_array; |
| 876 | niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array); |
| 877 | break; |
Lokesh Vutla | 69483e6 | 2017-12-29 11:47:51 +0530 | [diff] [blame] | 878 | case DRA762_ACD_ES1_0: |
Lokesh Vutla | 7e7d476 | 2017-08-21 12:50:56 +0530 | [diff] [blame] | 879 | case DRA762_ES1_0: |
| 880 | pads = dra76x_core_padconf_array; |
| 881 | npads = ARRAY_SIZE(dra76x_core_padconf_array); |
| 882 | iodelay = dra76x_es1_0_iodelay_cfg_array; |
| 883 | niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array); |
| 884 | break; |
Nishanth Menon | 6759e7f | 2015-08-13 09:50:59 -0500 | [diff] [blame] | 885 | default: |
| 886 | case DRA752_ES2_0: |
Lokesh Vutla | 69483e6 | 2017-12-29 11:47:51 +0530 | [diff] [blame] | 887 | case DRA762_ABZ_ES1_0: |
Nishanth Menon | 6759e7f | 2015-08-13 09:50:59 -0500 | [diff] [blame] | 888 | pads = dra74x_core_padconf_array; |
| 889 | npads = ARRAY_SIZE(dra74x_core_padconf_array); |
| 890 | iodelay = dra742_es2_0_iodelay_cfg_array; |
| 891 | niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array); |
Nishanth Menon | be3a553 | 2015-08-13 09:51:00 -0500 | [diff] [blame] | 892 | /* Setup port1 and port2 for rgmii with 'no-id' mode */ |
| 893 | clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK | |
| 894 | RGMII1_ID_MODE_N_MASK); |
Nishanth Menon | 6759e7f | 2015-08-13 09:50:59 -0500 | [diff] [blame] | 895 | break; |
Nishanth Menon | 97313b5 | 2015-06-04 16:42:39 +0530 | [diff] [blame] | 896 | } |
Nishanth Menon | d3b7d85 | 2016-03-15 18:09:17 -0500 | [diff] [blame] | 897 | /* Setup I/O isolation */ |
| 898 | ret = __recalibrate_iodelay_start(); |
| 899 | if (ret) |
| 900 | goto err; |
| 901 | |
| 902 | /* Do the muxing here */ |
| 903 | do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads); |
| 904 | |
| 905 | /* Now do the weird minor deltas that should be safe */ |
| 906 | if (delta_npads) |
| 907 | do_set_mux32((*ctrl)->control_padconf_core_base, |
| 908 | delta_pads, delta_npads); |
| 909 | |
Vignesh R | 0e0835e | 2017-12-12 17:14:27 +0530 | [diff] [blame] | 910 | if (is_dra76x()) |
| 911 | /* Set mux for MCAN instead of DCAN1 */ |
| 912 | clrsetbits_le32((*ctrl)->control_core_control_spare_rw, |
| 913 | MCAN_SEL_ALT_MASK, MCAN_SEL); |
| 914 | |
Nishanth Menon | d3b7d85 | 2016-03-15 18:09:17 -0500 | [diff] [blame] | 915 | /* Setup IOdelay configuration */ |
| 916 | ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); |
| 917 | err: |
| 918 | /* Closeup.. remove isolation */ |
| 919 | __recalibrate_iodelay_end(ret); |
Lokesh Vutla | 1fd8022 | 2015-06-04 16:42:38 +0530 | [diff] [blame] | 920 | } |
| 921 | #endif |
| 922 | |
Masahiro Yamada | 0a78017 | 2017-05-09 20:31:39 +0900 | [diff] [blame] | 923 | #if defined(CONFIG_MMC) |
Lokesh Vutla | 40700ad | 2013-02-12 21:29:08 +0000 | [diff] [blame] | 924 | int board_mmc_init(bd_t *bis) |
| 925 | { |
| 926 | omap_mmc_init(0, 0, 0, -1, -1); |
| 927 | omap_mmc_init(1, 0, 0, -1, -1); |
| 928 | return 0; |
| 929 | } |
Lokesh Vutla | 8352d27 | 2017-08-21 12:50:49 +0530 | [diff] [blame] | 930 | |
| 931 | void board_mmc_poweron_ldo(uint voltage) |
| 932 | { |
| 933 | if (board_is_dra71x_evm()) { |
| 934 | if (voltage == LDO_VOLT_3V0) |
| 935 | voltage = 0x19; |
| 936 | else if (voltage == LDO_VOLT_1V8) |
| 937 | voltage = 0xa; |
| 938 | lp873x_mmc1_poweron_ldo(voltage); |
Lokesh Vutla | 4712cc4 | 2017-08-21 12:50:57 +0530 | [diff] [blame] | 939 | } else if (board_is_dra76x_evm()) { |
| 940 | palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage); |
Lokesh Vutla | 8352d27 | 2017-08-21 12:50:49 +0530 | [diff] [blame] | 941 | } else { |
Lokesh Vutla | 22fa819 | 2017-08-21 12:50:50 +0530 | [diff] [blame] | 942 | palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage); |
Lokesh Vutla | 8352d27 | 2017-08-21 12:50:49 +0530 | [diff] [blame] | 943 | } |
| 944 | } |
Kishon Vijay Abraham I | 110ed01 | 2018-01-30 16:01:52 +0100 | [diff] [blame] | 945 | |
| 946 | static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = { |
| 947 | .hw_rev = "rev11", |
| 948 | .unsupported_caps = MMC_CAP(MMC_HS_200) | |
| 949 | MMC_CAP(UHS_SDR104), |
| 950 | .max_freq = 96000000, |
| 951 | }; |
| 952 | |
| 953 | static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = { |
| 954 | .hw_rev = "rev11", |
| 955 | .unsupported_caps = MMC_CAP(MMC_HS_200) | |
| 956 | MMC_CAP(UHS_SDR104) | |
| 957 | MMC_CAP(UHS_SDR50), |
| 958 | .max_freq = 48000000, |
| 959 | }; |
| 960 | |
| 961 | const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) |
| 962 | { |
| 963 | switch (omap_revision()) { |
| 964 | case DRA752_ES1_0: |
| 965 | case DRA752_ES1_1: |
| 966 | if (addr == OMAP_HSMMC1_BASE) |
| 967 | return &dra7x_es1_1_mmc1_fixups; |
| 968 | else |
| 969 | return &dra7x_es1_1_mmc23_fixups; |
| 970 | default: |
| 971 | return NULL; |
| 972 | } |
| 973 | } |
Lokesh Vutla | 40700ad | 2013-02-12 21:29:08 +0000 | [diff] [blame] | 974 | #endif |
Mugunthan V N | ab48f78 | 2013-07-08 16:04:41 +0530 | [diff] [blame] | 975 | |
Tom Rini | 560ef45 | 2014-04-03 07:52:56 -0400 | [diff] [blame] | 976 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) |
| 977 | int spl_start_uboot(void) |
| 978 | { |
| 979 | /* break into full u-boot on 'c' */ |
| 980 | if (serial_tstc() && serial_getc() == 'c') |
| 981 | return 1; |
| 982 | |
| 983 | #ifdef CONFIG_SPL_ENV_SUPPORT |
| 984 | env_init(); |
Simon Glass | 1753957 | 2017-08-03 12:22:07 -0600 | [diff] [blame] | 985 | env_load(); |
Simon Glass | 22c34c2 | 2017-08-03 12:22:13 -0600 | [diff] [blame] | 986 | if (env_get_yesno("boot_os") != 1) |
Tom Rini | 560ef45 | 2014-04-03 07:52:56 -0400 | [diff] [blame] | 987 | return 1; |
| 988 | #endif |
| 989 | |
| 990 | return 0; |
| 991 | } |
| 992 | #endif |
| 993 | |
Mugunthan V N | ab48f78 | 2013-07-08 16:04:41 +0530 | [diff] [blame] | 994 | #ifdef CONFIG_DRIVER_TI_CPSW |
Mugunthan V N | de170b3 | 2014-05-22 14:37:12 +0530 | [diff] [blame] | 995 | extern u32 *const omap_si_rev; |
| 996 | |
Mugunthan V N | ab48f78 | 2013-07-08 16:04:41 +0530 | [diff] [blame] | 997 | static void cpsw_control(int enabled) |
| 998 | { |
| 999 | /* VTP can be added here */ |
| 1000 | |
| 1001 | return; |
| 1002 | } |
| 1003 | |
| 1004 | static struct cpsw_slave_data cpsw_slaves[] = { |
| 1005 | { |
| 1006 | .slave_reg_ofs = 0x208, |
| 1007 | .sliver_reg_ofs = 0xd80, |
Mugunthan V N | 4944f37 | 2014-02-18 07:31:52 -0500 | [diff] [blame] | 1008 | .phy_addr = 2, |
Mugunthan V N | ab48f78 | 2013-07-08 16:04:41 +0530 | [diff] [blame] | 1009 | }, |
| 1010 | { |
| 1011 | .slave_reg_ofs = 0x308, |
| 1012 | .sliver_reg_ofs = 0xdc0, |
Mugunthan V N | 4944f37 | 2014-02-18 07:31:52 -0500 | [diff] [blame] | 1013 | .phy_addr = 3, |
Mugunthan V N | ab48f78 | 2013-07-08 16:04:41 +0530 | [diff] [blame] | 1014 | }, |
| 1015 | }; |
| 1016 | |
| 1017 | static struct cpsw_platform_data cpsw_data = { |
| 1018 | .mdio_base = CPSW_MDIO_BASE, |
| 1019 | .cpsw_base = CPSW_BASE, |
| 1020 | .mdio_div = 0xff, |
| 1021 | .channels = 8, |
| 1022 | .cpdma_reg_ofs = 0x800, |
Mugunthan V N | de170b3 | 2014-05-22 14:37:12 +0530 | [diff] [blame] | 1023 | .slaves = 2, |
Mugunthan V N | ab48f78 | 2013-07-08 16:04:41 +0530 | [diff] [blame] | 1024 | .slave_data = cpsw_slaves, |
| 1025 | .ale_reg_ofs = 0xd00, |
| 1026 | .ale_entries = 1024, |
| 1027 | .host_port_reg_ofs = 0x108, |
| 1028 | .hw_stats_reg_ofs = 0x900, |
| 1029 | .bd_ram_ofs = 0x2000, |
| 1030 | .mac_control = (1 << 5), |
| 1031 | .control = cpsw_control, |
| 1032 | .host_port_num = 0, |
| 1033 | .version = CPSW_CTRL_VERSION_2, |
| 1034 | }; |
| 1035 | |
| 1036 | int board_eth_init(bd_t *bis) |
| 1037 | { |
| 1038 | int ret; |
| 1039 | uint8_t mac_addr[6]; |
| 1040 | uint32_t mac_hi, mac_lo; |
| 1041 | uint32_t ctrl_val; |
Mugunthan V N | ab48f78 | 2013-07-08 16:04:41 +0530 | [diff] [blame] | 1042 | |
| 1043 | /* try reading mac address from efuse */ |
| 1044 | mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); |
| 1045 | mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); |
Mugunthan V N | f8b45c2 | 2014-01-07 19:57:38 +0530 | [diff] [blame] | 1046 | mac_addr[0] = (mac_hi & 0xFF0000) >> 16; |
Mugunthan V N | ab48f78 | 2013-07-08 16:04:41 +0530 | [diff] [blame] | 1047 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
Mugunthan V N | f8b45c2 | 2014-01-07 19:57:38 +0530 | [diff] [blame] | 1048 | mac_addr[2] = mac_hi & 0xFF; |
| 1049 | mac_addr[3] = (mac_lo & 0xFF0000) >> 16; |
Mugunthan V N | ab48f78 | 2013-07-08 16:04:41 +0530 | [diff] [blame] | 1050 | mac_addr[4] = (mac_lo & 0xFF00) >> 8; |
Mugunthan V N | f8b45c2 | 2014-01-07 19:57:38 +0530 | [diff] [blame] | 1051 | mac_addr[5] = mac_lo & 0xFF; |
Mugunthan V N | ab48f78 | 2013-07-08 16:04:41 +0530 | [diff] [blame] | 1052 | |
Simon Glass | 64b723f | 2017-08-03 12:22:12 -0600 | [diff] [blame] | 1053 | if (!env_get("ethaddr")) { |
Mugunthan V N | ab48f78 | 2013-07-08 16:04:41 +0530 | [diff] [blame] | 1054 | printf("<ethaddr> not set. Validating first E-fuse MAC\n"); |
| 1055 | |
Joe Hershberger | 8ecdbed | 2015-04-08 01:41:04 -0500 | [diff] [blame] | 1056 | if (is_valid_ethaddr(mac_addr)) |
Simon Glass | 8551d55 | 2017-08-03 12:22:11 -0600 | [diff] [blame] | 1057 | eth_env_set_enetaddr("ethaddr", mac_addr); |
Mugunthan V N | ab48f78 | 2013-07-08 16:04:41 +0530 | [diff] [blame] | 1058 | } |
Mugunthan V N | 1991b5c | 2014-02-18 07:31:56 -0500 | [diff] [blame] | 1059 | |
| 1060 | mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); |
| 1061 | mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); |
| 1062 | mac_addr[0] = (mac_hi & 0xFF0000) >> 16; |
| 1063 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
| 1064 | mac_addr[2] = mac_hi & 0xFF; |
| 1065 | mac_addr[3] = (mac_lo & 0xFF0000) >> 16; |
| 1066 | mac_addr[4] = (mac_lo & 0xFF00) >> 8; |
| 1067 | mac_addr[5] = mac_lo & 0xFF; |
| 1068 | |
Simon Glass | 64b723f | 2017-08-03 12:22:12 -0600 | [diff] [blame] | 1069 | if (!env_get("eth1addr")) { |
Joe Hershberger | 8ecdbed | 2015-04-08 01:41:04 -0500 | [diff] [blame] | 1070 | if (is_valid_ethaddr(mac_addr)) |
Simon Glass | 8551d55 | 2017-08-03 12:22:11 -0600 | [diff] [blame] | 1071 | eth_env_set_enetaddr("eth1addr", mac_addr); |
Mugunthan V N | 1991b5c | 2014-02-18 07:31:56 -0500 | [diff] [blame] | 1072 | } |
| 1073 | |
Mugunthan V N | ab48f78 | 2013-07-08 16:04:41 +0530 | [diff] [blame] | 1074 | ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); |
| 1075 | ctrl_val |= 0x22; |
| 1076 | writel(ctrl_val, (*ctrl)->control_core_control_io1); |
| 1077 | |
Mugunthan V N | de170b3 | 2014-05-22 14:37:12 +0530 | [diff] [blame] | 1078 | if (*omap_si_rev == DRA722_ES1_0) |
| 1079 | cpsw_data.active_slave = 1; |
| 1080 | |
Dan Murphy | b1941f3 | 2016-03-30 12:58:37 -0500 | [diff] [blame] | 1081 | if (board_is_dra72x_revc_or_later()) { |
| 1082 | cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID; |
| 1083 | cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID; |
| 1084 | } |
| 1085 | |
Mugunthan V N | ab48f78 | 2013-07-08 16:04:41 +0530 | [diff] [blame] | 1086 | ret = cpsw_register(&cpsw_data); |
| 1087 | if (ret < 0) |
| 1088 | printf("Error %d registering CPSW switch\n", ret); |
| 1089 | |
| 1090 | return ret; |
| 1091 | } |
| 1092 | #endif |
Lokesh Vutla | be86f0e | 2014-08-04 19:42:24 +0530 | [diff] [blame] | 1093 | |
| 1094 | #ifdef CONFIG_BOARD_EARLY_INIT_F |
| 1095 | /* VTT regulator enable */ |
| 1096 | static inline void vtt_regulator_enable(void) |
| 1097 | { |
| 1098 | if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) |
| 1099 | return; |
| 1100 | |
Lokesh Vutla | 6f1038f | 2017-08-21 12:50:55 +0530 | [diff] [blame] | 1101 | /* Do not enable VTT for DRA722 or DRA76x */ |
| 1102 | if (is_dra72x() || is_dra76x()) |
Lokesh Vutla | be86f0e | 2014-08-04 19:42:24 +0530 | [diff] [blame] | 1103 | return; |
| 1104 | |
| 1105 | /* |
| 1106 | * EVM Rev G and later use gpio7_11 for DDR3 termination. |
| 1107 | * This is safe enough to do on older revs. |
| 1108 | */ |
| 1109 | gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); |
| 1110 | gpio_direction_output(GPIO_DDR_VTT_EN, 1); |
| 1111 | } |
| 1112 | |
| 1113 | int board_early_init_f(void) |
| 1114 | { |
| 1115 | vtt_regulator_enable(); |
| 1116 | return 0; |
| 1117 | } |
| 1118 | #endif |
Daniel Allred | 7ceffb2 | 2016-05-19 19:10:54 -0500 | [diff] [blame] | 1119 | |
| 1120 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) |
| 1121 | int ft_board_setup(void *blob, bd_t *bd) |
| 1122 | { |
| 1123 | ft_cpu_setup(blob, bd); |
| 1124 | |
| 1125 | return 0; |
| 1126 | } |
| 1127 | #endif |
Lokesh Vutla | f4de472 | 2016-05-16 10:51:23 +0530 | [diff] [blame] | 1128 | |
| 1129 | #ifdef CONFIG_SPL_LOAD_FIT |
| 1130 | int board_fit_config_name_match(const char *name) |
| 1131 | { |
Mugunthan V N | b8c6b02 | 2016-09-27 13:01:41 +0530 | [diff] [blame] | 1132 | if (is_dra72x()) { |
Lokesh Vutla | f0d5517 | 2016-11-23 13:25:30 +0530 | [diff] [blame] | 1133 | if (board_is_dra71x_evm()) { |
| 1134 | if (!strcmp(name, "dra71-evm")) |
| 1135 | return 0; |
| 1136 | }else if(board_is_dra72x_revc_or_later()) { |
Mugunthan V N | b8c6b02 | 2016-09-27 13:01:41 +0530 | [diff] [blame] | 1137 | if (!strcmp(name, "dra72-evm-revc")) |
| 1138 | return 0; |
| 1139 | } else if (!strcmp(name, "dra72-evm")) { |
| 1140 | return 0; |
| 1141 | } |
Lokesh Vutla | 69483e6 | 2017-12-29 11:47:51 +0530 | [diff] [blame] | 1142 | } else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) { |
Lokesh Vutla | 635848f | 2017-08-21 12:51:01 +0530 | [diff] [blame] | 1143 | return 0; |
Lokesh Vutla | 69483e6 | 2017-12-29 11:47:51 +0530 | [diff] [blame] | 1144 | } else if (!is_dra72x() && !is_dra76x_acd() && |
| 1145 | !strcmp(name, "dra7-evm")) { |
Lokesh Vutla | f4de472 | 2016-05-16 10:51:23 +0530 | [diff] [blame] | 1146 | return 0; |
Mugunthan V N | b8c6b02 | 2016-09-27 13:01:41 +0530 | [diff] [blame] | 1147 | } |
| 1148 | |
| 1149 | return -1; |
Lokesh Vutla | f4de472 | 2016-05-16 10:51:23 +0530 | [diff] [blame] | 1150 | } |
| 1151 | #endif |
Andreas Dannenberg | 5cf344b | 2016-06-27 09:19:22 -0500 | [diff] [blame] | 1152 | |
Andrew F. Davis | d355583 | 2019-02-11 08:00:08 -0600 | [diff] [blame] | 1153 | #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE) |
| 1154 | int fastboot_set_reboot_flag(void) |
| 1155 | { |
| 1156 | printf("Setting reboot to fastboot flag ...\n"); |
| 1157 | env_set("dofastboot", "1"); |
| 1158 | env_save(); |
| 1159 | return 0; |
| 1160 | } |
| 1161 | #endif |
| 1162 | |
Andreas Dannenberg | 5cf344b | 2016-06-27 09:19:22 -0500 | [diff] [blame] | 1163 | #ifdef CONFIG_TI_SECURE_DEVICE |
| 1164 | void board_fit_image_post_process(void **p_image, size_t *p_size) |
| 1165 | { |
| 1166 | secure_boot_verify_image(p_image, p_size); |
| 1167 | } |
Andrew F. Davis | d216a4c | 2016-11-29 16:33:25 -0600 | [diff] [blame] | 1168 | |
| 1169 | void board_tee_image_process(ulong tee_image, size_t tee_size) |
| 1170 | { |
| 1171 | secure_tee_install((u32)tee_image); |
| 1172 | } |
| 1173 | |
| 1174 | U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process); |
Andreas Dannenberg | 5cf344b | 2016-06-27 09:19:22 -0500 | [diff] [blame] | 1175 | #endif |