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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenke65527f2004-02-12 00:47:09 +00002/*
wdenke65527f2004-02-12 00:47:09 +00003 * (C) Copyright 2000-2004
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
Alison Wang95bed1f2012-03-26 21:49:04 +00006 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
TsiChungLiew34674692007-08-16 13:20:50 -05007 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
wdenke65527f2004-02-12 00:47:09 +00008 */
9
10#include <common.h>
Simon Glass9b61c7c2019-11-14 12:57:41 -070011#include <irq_func.h>
wdenke65527f2004-02-12 00:47:09 +000012#include <watchdog.h>
13#include <asm/processor.h>
TsiChungLiew8cd73be2007-08-15 19:21:21 -050014#include <asm/immap.h>
Alison Wang95bed1f2012-03-26 21:49:04 +000015#include <asm/io.h>
Zachary P. Landau0bba8622006-01-26 17:35:56 -050016
wdenke65527f2004-02-12 00:47:09 +000017#ifdef CONFIG_M5272
TsiChungLiew8cd73be2007-08-15 19:21:21 -050018int interrupt_init(void)
wdenke65527f2004-02-12 00:47:09 +000019{
Alison Wang95bed1f2012-03-26 21:49:04 +000020 intctrl_t *intp = (intctrl_t *) (MMAP_INTC);
wdenke65527f2004-02-12 00:47:09 +000021
TsiChungLiew8cd73be2007-08-15 19:21:21 -050022 /* disable all external interrupts */
Alison Wang95bed1f2012-03-26 21:49:04 +000023 out_be32(&intp->int_icr1, 0x88888888);
24 out_be32(&intp->int_icr2, 0x88888888);
25 out_be32(&intp->int_icr3, 0x88888888);
26 out_be32(&intp->int_icr4, 0x88888888);
27 out_be32(&intp->int_pitr, 0x00000000);
28
TsiChungLiew8cd73be2007-08-15 19:21:21 -050029 /* initialize vector register */
Alison Wang95bed1f2012-03-26 21:49:04 +000030 out_8(&intp->int_pivr, 0x40);
wdenke65527f2004-02-12 00:47:09 +000031
TsiChungLiew8cd73be2007-08-15 19:21:21 -050032 enable_interrupts();
wdenke65527f2004-02-12 00:47:09 +000033
TsiChungLiew8cd73be2007-08-15 19:21:21 -050034 return 0;
wdenke65527f2004-02-12 00:47:09 +000035}
36
TsiChungLiew8cd73be2007-08-15 19:21:21 -050037#if defined(CONFIG_MCFTMR)
38void dtimer_intr_setup(void)
wdenke65527f2004-02-12 00:47:09 +000039{
Alison Wang95bed1f2012-03-26 21:49:04 +000040 intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
wdenke65527f2004-02-12 00:47:09 +000041
Alison Wang95bed1f2012-03-26 21:49:04 +000042 clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
43 setbits_be32(&intp->int_icr1, CONFIG_SYS_TMRINTR_PRI);
wdenke65527f2004-02-12 00:47:09 +000044}
TsiChungLiew8cd73be2007-08-15 19:21:21 -050045#endif /* CONFIG_MCFTMR */
46#endif /* CONFIG_M5272 */
wdenke65527f2004-02-12 00:47:09 +000047
TsiChung Liewb354aef2009-06-12 11:29:00 +000048#if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \
49 defined(CONFIG_M5271) || defined(CONFIG_M5275)
TsiChungLiew8cd73be2007-08-15 19:21:21 -050050int interrupt_init(void)
wdenke65527f2004-02-12 00:47:09 +000051{
Alison Wang95bed1f2012-03-26 21:49:04 +000052 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
wdenke65527f2004-02-12 00:47:09 +000053
TsiChungLiew8cd73be2007-08-15 19:21:21 -050054 /* Make sure all interrupts are disabled */
TsiChung Liewb354aef2009-06-12 11:29:00 +000055#if defined(CONFIG_M5208)
Alison Wang95bed1f2012-03-26 21:49:04 +000056 out_be32(&intp->imrl0, 0xffffffff);
57 out_be32(&intp->imrh0, 0xffffffff);
TsiChung Liewb354aef2009-06-12 11:29:00 +000058#else
Alison Wang95bed1f2012-03-26 21:49:04 +000059 setbits_be32(&intp->imrl0, 0x1);
TsiChung Liewb354aef2009-06-12 11:29:00 +000060#endif
wdenke65527f2004-02-12 00:47:09 +000061
TsiChungLiew8cd73be2007-08-15 19:21:21 -050062 enable_interrupts();
63 return 0;
wdenke65527f2004-02-12 00:47:09 +000064}
65
TsiChungLiew8cd73be2007-08-15 19:21:21 -050066#if defined(CONFIG_MCFTMR)
67void dtimer_intr_setup(void)
wdenke65527f2004-02-12 00:47:09 +000068{
Alison Wang95bed1f2012-03-26 21:49:04 +000069 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
wdenke65527f2004-02-12 00:47:09 +000070
Alison Wang95bed1f2012-03-26 21:49:04 +000071 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
72 clrbits_be32(&intp->imrl0, 0x00000001);
73 clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
wdenke65527f2004-02-12 00:47:09 +000074}
TsiChungLiew8cd73be2007-08-15 19:21:21 -050075#endif /* CONFIG_MCFTMR */
Matthew Fettke761e2e92008-02-04 15:38:20 -060076#endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
wdenke65527f2004-02-12 00:47:09 +000077
TsiChungLiew34674692007-08-16 13:20:50 -050078#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
TsiChungLiew8cd73be2007-08-15 19:21:21 -050079int interrupt_init(void)
wdenke65527f2004-02-12 00:47:09 +000080{
TsiChungLiew8cd73be2007-08-15 19:21:21 -050081 enable_interrupts();
wdenke65527f2004-02-12 00:47:09 +000082
83 return 0;
84}
wdenke65527f2004-02-12 00:47:09 +000085
TsiChungLiew8cd73be2007-08-15 19:21:21 -050086#if defined(CONFIG_MCFTMR)
87void dtimer_intr_setup(void)
wdenke65527f2004-02-12 00:47:09 +000088{
TsiChungLiew8cd73be2007-08-15 19:21:21 -050089 mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020090 mbar_writeByte(MCFSIM_TIMER2ICR, CONFIG_SYS_TMRINTR_PRI);
stroese53395a22004-12-16 18:09:49 +000091}
TsiChungLiew8cd73be2007-08-15 19:21:21 -050092#endif /* CONFIG_MCFTMR */
TsiChungLiew34674692007-08-16 13:20:50 -050093#endif /* CONFIG_M5249 || CONFIG_M5253 */