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git01.mediatek.com / filogic / uboot / 523bc4d971164a0a1cabfaeaeef5b33f9a87495a / . / arch / arm / mach-apple / board.c
blob: 0b6d290b8ac41eea14455b920475e2086f77ccc1 [file] [log] [blame]
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org>
4 */
5
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]6#include <dm.h>
Mark Kettenisdfacafb2022-04-19 21:20:31 +0200[diff] [blame]7#include <dm/uclass-internal.h>
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]8#include <efi_loader.h>
Mark Kettenis74ec0482022-03-21 22:41:18 +0100[diff] [blame]9#include <lmb.h>
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]10
11#include <asm/armv8/mmu.h>
12#include <asm/global_data.h>
13#include <asm/io.h>
14#include <asm/system.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
Janne Grunau430ff522022-07-01 00:06:17 +0200[diff] [blame]18/* Apple M1/M2 */
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]19
20static struct mm_region t8103_mem_map[] = {
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]21 {
22 /* I/O */
23 .virt = 0x200000000,
24 .phys = 0x200000000,
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]25 .size = 2UL * SZ_1G,
26 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
27 PTE_BLOCK_NON_SHARE |
28 PTE_BLOCK_PXN | PTE_BLOCK_UXN
29 }, {
30 /* I/O */
31 .virt = 0x380000000,
32 .phys = 0x380000000,
33 .size = SZ_1G,
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]34 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
35 PTE_BLOCK_NON_SHARE |
36 PTE_BLOCK_PXN | PTE_BLOCK_UXN
37 }, {
38 /* I/O */
39 .virt = 0x500000000,
40 .phys = 0x500000000,
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]41 .size = SZ_1G,
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]42 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
43 PTE_BLOCK_NON_SHARE |
44 PTE_BLOCK_PXN | PTE_BLOCK_UXN
45 }, {
46 /* I/O */
47 .virt = 0x680000000,
48 .phys = 0x680000000,
49 .size = SZ_512M,
50 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
51 PTE_BLOCK_NON_SHARE |
52 PTE_BLOCK_PXN | PTE_BLOCK_UXN
53 }, {
54 /* PCIE */
55 .virt = 0x6a0000000,
56 .phys = 0x6a0000000,
57 .size = SZ_512M,
58 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
59 PTE_BLOCK_INNER_SHARE |
60 PTE_BLOCK_PXN | PTE_BLOCK_UXN
61 }, {
62 /* PCIE */
63 .virt = 0x6c0000000,
64 .phys = 0x6c0000000,
65 .size = SZ_1G,
66 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
67 PTE_BLOCK_INNER_SHARE |
68 PTE_BLOCK_PXN | PTE_BLOCK_UXN
69 }, {
70 /* RAM */
71 .virt = 0x800000000,
72 .phys = 0x800000000,
73 .size = 8UL * SZ_1G,
74 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
75 PTE_BLOCK_INNER_SHARE
76 }, {
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]77 /* Framebuffer */
78 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
79 PTE_BLOCK_INNER_SHARE |
80 PTE_BLOCK_PXN | PTE_BLOCK_UXN
81 }, {
82 /* List terminator */
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]83 0,
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]84 }
85};
86
87/* Apple M1 Pro/Max */
88
89static struct mm_region t6000_mem_map[] = {
90 {
91 /* I/O */
92 .virt = 0x280000000,
93 .phys = 0x280000000,
94 .size = SZ_1G,
95 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
96 PTE_BLOCK_NON_SHARE |
97 PTE_BLOCK_PXN | PTE_BLOCK_UXN
98 }, {
99 /* I/O */
100 .virt = 0x380000000,
101 .phys = 0x380000000,
102 .size = SZ_1G,
103 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
104 PTE_BLOCK_NON_SHARE |
105 PTE_BLOCK_PXN | PTE_BLOCK_UXN
106 }, {
107 /* I/O */
108 .virt = 0x580000000,
109 .phys = 0x580000000,
110 .size = SZ_512M,
111 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
112 PTE_BLOCK_NON_SHARE |
113 PTE_BLOCK_PXN | PTE_BLOCK_UXN
114 }, {
115 /* PCIE */
116 .virt = 0x5a0000000,
117 .phys = 0x5a0000000,
118 .size = SZ_512M,
119 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
120 PTE_BLOCK_INNER_SHARE |
121 PTE_BLOCK_PXN | PTE_BLOCK_UXN
122 }, {
123 /* PCIE */
124 .virt = 0x5c0000000,
125 .phys = 0x5c0000000,
126 .size = SZ_1G,
127 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
128 PTE_BLOCK_INNER_SHARE |
129 PTE_BLOCK_PXN | PTE_BLOCK_UXN
130 }, {
131 /* I/O */
132 .virt = 0x700000000,
133 .phys = 0x700000000,
134 .size = SZ_1G,
135 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
136 PTE_BLOCK_NON_SHARE |
137 PTE_BLOCK_PXN | PTE_BLOCK_UXN
138 }, {
139 /* I/O */
140 .virt = 0xb00000000,
141 .phys = 0xb00000000,
142 .size = SZ_1G,
143 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
144 PTE_BLOCK_NON_SHARE |
145 PTE_BLOCK_PXN | PTE_BLOCK_UXN
146 }, {
147 /* I/O */
148 .virt = 0xf00000000,
149 .phys = 0xf00000000,
150 .size = SZ_1G,
151 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
152 PTE_BLOCK_NON_SHARE |
153 PTE_BLOCK_PXN | PTE_BLOCK_UXN
154 }, {
155 /* I/O */
156 .virt = 0x1300000000,
157 .phys = 0x1300000000,
158 .size = SZ_1G,
159 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
160 PTE_BLOCK_NON_SHARE |
161 PTE_BLOCK_PXN | PTE_BLOCK_UXN
162 }, {
163 /* RAM */
164 .virt = 0x10000000000,
165 .phys = 0x10000000000,
166 .size = 16UL * SZ_1G,
167 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
168 PTE_BLOCK_INNER_SHARE
169 }, {
170 /* Framebuffer */
171 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
172 PTE_BLOCK_INNER_SHARE |
173 PTE_BLOCK_PXN | PTE_BLOCK_UXN
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]174 }, {
175 /* List terminator */
176 0,
177 }
178};
179
Janne Grunaudc174322022-03-29 13:29:35 +0200[diff] [blame]180/* Apple M1 Ultra */
181
182static struct mm_region t6002_mem_map[] = {
183 {
184 /* I/O */
185 .virt = 0x280000000,
186 .phys = 0x280000000,
187 .size = SZ_1G,
188 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
189 PTE_BLOCK_NON_SHARE |
190 PTE_BLOCK_PXN | PTE_BLOCK_UXN
191 }, {
192 /* I/O */
193 .virt = 0x380000000,
194 .phys = 0x380000000,
195 .size = SZ_1G,
196 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
197 PTE_BLOCK_NON_SHARE |
198 PTE_BLOCK_PXN | PTE_BLOCK_UXN
199 }, {
200 /* I/O */
201 .virt = 0x580000000,
202 .phys = 0x580000000,
203 .size = SZ_512M,
204 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
205 PTE_BLOCK_NON_SHARE |
206 PTE_BLOCK_PXN | PTE_BLOCK_UXN
207 }, {
208 /* PCIE */
209 .virt = 0x5a0000000,
210 .phys = 0x5a0000000,
211 .size = SZ_512M,
212 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
213 PTE_BLOCK_INNER_SHARE |
214 PTE_BLOCK_PXN | PTE_BLOCK_UXN
215 }, {
216 /* PCIE */
217 .virt = 0x5c0000000,
218 .phys = 0x5c0000000,
219 .size = SZ_1G,
220 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
221 PTE_BLOCK_INNER_SHARE |
222 PTE_BLOCK_PXN | PTE_BLOCK_UXN
223 }, {
224 /* I/O */
225 .virt = 0x700000000,
226 .phys = 0x700000000,
227 .size = SZ_1G,
228 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
229 PTE_BLOCK_NON_SHARE |
230 PTE_BLOCK_PXN | PTE_BLOCK_UXN
231 }, {
232 /* I/O */
233 .virt = 0xb00000000,
234 .phys = 0xb00000000,
235 .size = SZ_1G,
236 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
237 PTE_BLOCK_NON_SHARE |
238 PTE_BLOCK_PXN | PTE_BLOCK_UXN
239 }, {
240 /* I/O */
241 .virt = 0xf00000000,
242 .phys = 0xf00000000,
243 .size = SZ_1G,
244 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
245 PTE_BLOCK_NON_SHARE |
246 PTE_BLOCK_PXN | PTE_BLOCK_UXN
247 }, {
248 /* I/O */
249 .virt = 0x1300000000,
250 .phys = 0x1300000000,
251 .size = SZ_1G,
252 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
253 PTE_BLOCK_NON_SHARE |
254 PTE_BLOCK_PXN | PTE_BLOCK_UXN
255 }, {
256 /* I/O */
257 .virt = 0x2280000000,
258 .phys = 0x2280000000,
259 .size = SZ_1G,
260 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
261 PTE_BLOCK_NON_SHARE |
262 PTE_BLOCK_PXN | PTE_BLOCK_UXN
263 }, {
264 /* I/O */
265 .virt = 0x2380000000,
266 .phys = 0x2380000000,
267 .size = SZ_1G,
268 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
269 PTE_BLOCK_NON_SHARE |
270 PTE_BLOCK_PXN | PTE_BLOCK_UXN
271 }, {
272 /* I/O */
273 .virt = 0x2580000000,
274 .phys = 0x2580000000,
275 .size = SZ_512M,
276 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
277 PTE_BLOCK_NON_SHARE |
278 PTE_BLOCK_PXN | PTE_BLOCK_UXN
279 }, {
280 /* PCIE */
281 .virt = 0x25a0000000,
282 .phys = 0x25a0000000,
283 .size = SZ_512M,
284 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
285 PTE_BLOCK_INNER_SHARE |
286 PTE_BLOCK_PXN | PTE_BLOCK_UXN
287 }, {
288 /* PCIE */
289 .virt = 0x25c0000000,
290 .phys = 0x25c0000000,
291 .size = SZ_1G,
292 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
293 PTE_BLOCK_INNER_SHARE |
294 PTE_BLOCK_PXN | PTE_BLOCK_UXN
295 }, {
296 /* I/O */
297 .virt = 0x2700000000,
298 .phys = 0x2700000000,
299 .size = SZ_1G,
300 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
301 PTE_BLOCK_NON_SHARE |
302 PTE_BLOCK_PXN | PTE_BLOCK_UXN
303 }, {
304 /* I/O */
305 .virt = 0x2b00000000,
306 .phys = 0x2b00000000,
307 .size = SZ_1G,
308 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
309 PTE_BLOCK_NON_SHARE |
310 PTE_BLOCK_PXN | PTE_BLOCK_UXN
311 }, {
312 /* I/O */
313 .virt = 0x2f00000000,
314 .phys = 0x2f00000000,
315 .size = SZ_1G,
316 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
317 PTE_BLOCK_NON_SHARE |
318 PTE_BLOCK_PXN | PTE_BLOCK_UXN
319 }, {
320 /* I/O */
321 .virt = 0x3300000000,
322 .phys = 0x3300000000,
323 .size = SZ_1G,
324 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
325 PTE_BLOCK_NON_SHARE |
326 PTE_BLOCK_PXN | PTE_BLOCK_UXN
327 }, {
328 /* RAM */
329 .virt = 0x10000000000,
330 .phys = 0x10000000000,
331 .size = 16UL * SZ_1G,
332 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
333 PTE_BLOCK_INNER_SHARE
334 }, {
335 /* Framebuffer */
336 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
337 PTE_BLOCK_INNER_SHARE |
338 PTE_BLOCK_PXN | PTE_BLOCK_UXN
339 }, {
340 /* List terminator */
341 0,
342 }
343};
344
Mark Kettenis1b350702023-05-02 21:30:40 +0200[diff] [blame]345/* Apple M2 Pro/Max */
346
347static struct mm_region t6020_mem_map[] = {
348 {
349 /* I/O */
350 .virt = 0x280000000,
351 .phys = 0x280000000,
352 .size = SZ_1G,
353 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
354 PTE_BLOCK_NON_SHARE |
355 PTE_BLOCK_PXN | PTE_BLOCK_UXN
356 }, {
357 /* I/O */
358 .virt = 0x340000000,
359 .phys = 0x340000000,
360 .size = SZ_1G,
361 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
362 PTE_BLOCK_NON_SHARE |
363 PTE_BLOCK_PXN | PTE_BLOCK_UXN
364 }, {
365 /* I/O */
366 .virt = 0x380000000,
367 .phys = 0x380000000,
368 .size = SZ_1G,
369 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
370 PTE_BLOCK_NON_SHARE |
371 PTE_BLOCK_PXN | PTE_BLOCK_UXN
372 }, {
373 /* I/O */
Janne Grunauefc0df02023-12-01 08:12:33 +0100[diff] [blame]374 .virt = 0x400000000,
375 .phys = 0x400000000,
376 .size = SZ_1G,
377 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
378 PTE_BLOCK_NON_SHARE |
379 PTE_BLOCK_PXN | PTE_BLOCK_UXN
380 }, {
381 /* I/O */
382 .virt = 0x480000000,
383 .phys = 0x480000000,
384 .size = SZ_1G,
385 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
386 PTE_BLOCK_NON_SHARE |
387 PTE_BLOCK_PXN | PTE_BLOCK_UXN
388 }, {
389 /* I/O */
Mark Kettenis1b350702023-05-02 21:30:40 +0200[diff] [blame]390 .virt = 0x580000000,
391 .phys = 0x580000000,
392 .size = SZ_512M,
393 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
394 PTE_BLOCK_NON_SHARE |
395 PTE_BLOCK_PXN | PTE_BLOCK_UXN
396 }, {
397 /* PCIE */
398 .virt = 0x5a0000000,
399 .phys = 0x5a0000000,
400 .size = SZ_512M,
401 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
402 PTE_BLOCK_INNER_SHARE |
403 PTE_BLOCK_PXN | PTE_BLOCK_UXN
404 }, {
405 /* PCIE */
406 .virt = 0x5c0000000,
407 .phys = 0x5c0000000,
408 .size = SZ_1G,
409 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
410 PTE_BLOCK_INNER_SHARE |
411 PTE_BLOCK_PXN | PTE_BLOCK_UXN
412 }, {
413 /* I/O */
414 .virt = 0x700000000,
415 .phys = 0x700000000,
416 .size = SZ_1G,
417 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
418 PTE_BLOCK_NON_SHARE |
419 PTE_BLOCK_PXN | PTE_BLOCK_UXN
420 }, {
421 /* I/O */
422 .virt = 0xb00000000,
423 .phys = 0xb00000000,
424 .size = SZ_1G,
425 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
426 PTE_BLOCK_NON_SHARE |
427 PTE_BLOCK_PXN | PTE_BLOCK_UXN
428 }, {
429 /* I/O */
430 .virt = 0xf00000000,
431 .phys = 0xf00000000,
432 .size = SZ_1G,
433 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
434 PTE_BLOCK_NON_SHARE |
435 PTE_BLOCK_PXN | PTE_BLOCK_UXN
436 }, {
437 /* I/O */
438 .virt = 0x1300000000,
439 .phys = 0x1300000000,
440 .size = SZ_1G,
441 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
442 PTE_BLOCK_NON_SHARE |
443 PTE_BLOCK_PXN | PTE_BLOCK_UXN
444 }, {
445 /* RAM */
446 .virt = 0x10000000000,
447 .phys = 0x10000000000,
448 .size = 16UL * SZ_1G,
449 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
450 PTE_BLOCK_INNER_SHARE
451 }, {
452 /* Framebuffer */
453 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
454 PTE_BLOCK_INNER_SHARE |
455 PTE_BLOCK_PXN | PTE_BLOCK_UXN
456 }, {
457 /* List terminator */
458 0,
459 }
460};
461
Janne Grunau19e1c482023-09-06 23:50:34 +0200[diff] [blame]462/* Apple M2 Ultra */
463
464static struct mm_region t6022_mem_map[] = {
465 {
466 /* I/O */
467 .virt = 0x280000000,
468 .phys = 0x280000000,
469 .size = SZ_1G,
470 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
471 PTE_BLOCK_NON_SHARE |
472 PTE_BLOCK_PXN | PTE_BLOCK_UXN
473 }, {
474 /* I/O */
475 .virt = 0x340000000,
476 .phys = 0x340000000,
477 .size = SZ_1G,
478 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
479 PTE_BLOCK_NON_SHARE |
480 PTE_BLOCK_PXN | PTE_BLOCK_UXN
481 }, {
482 /* I/O */
483 .virt = 0x380000000,
484 .phys = 0x380000000,
485 .size = SZ_1G,
486 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
487 PTE_BLOCK_NON_SHARE |
488 PTE_BLOCK_PXN | PTE_BLOCK_UXN
489 }, {
490 /* I/O */
Janne Grunauefc0df02023-12-01 08:12:33 +0100[diff] [blame]491 .virt = 0x400000000,
492 .phys = 0x400000000,
493 .size = SZ_1G,
494 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
495 PTE_BLOCK_NON_SHARE |
496 PTE_BLOCK_PXN | PTE_BLOCK_UXN
497 }, {
498 /* I/O */
499 .virt = 0x480000000,
500 .phys = 0x480000000,
501 .size = SZ_1G,
502 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
503 PTE_BLOCK_NON_SHARE |
504 PTE_BLOCK_PXN | PTE_BLOCK_UXN
505 }, {
506 /* I/O */
Janne Grunau19e1c482023-09-06 23:50:34 +0200[diff] [blame]507 .virt = 0x580000000,
508 .phys = 0x580000000,
509 .size = SZ_512M,
510 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
511 PTE_BLOCK_NON_SHARE |
512 PTE_BLOCK_PXN | PTE_BLOCK_UXN
513 }, {
514 /* PCIE */
515 .virt = 0x5a0000000,
516 .phys = 0x5a0000000,
517 .size = SZ_512M,
518 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
519 PTE_BLOCK_INNER_SHARE |
520 PTE_BLOCK_PXN | PTE_BLOCK_UXN
521 }, {
522 /* PCIE */
523 .virt = 0x5c0000000,
524 .phys = 0x5c0000000,
525 .size = SZ_1G,
526 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
527 PTE_BLOCK_INNER_SHARE |
528 PTE_BLOCK_PXN | PTE_BLOCK_UXN
529 }, {
530 /* I/O */
531 .virt = 0x700000000,
532 .phys = 0x700000000,
533 .size = SZ_1G,
534 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
535 PTE_BLOCK_NON_SHARE |
536 PTE_BLOCK_PXN | PTE_BLOCK_UXN
537 }, {
538 /* I/O */
539 .virt = 0xb00000000,
540 .phys = 0xb00000000,
541 .size = SZ_1G,
542 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
543 PTE_BLOCK_NON_SHARE |
544 PTE_BLOCK_PXN | PTE_BLOCK_UXN
545 }, {
546 /* I/O */
547 .virt = 0xf00000000,
548 .phys = 0xf00000000,
549 .size = SZ_1G,
550 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
551 PTE_BLOCK_NON_SHARE |
552 PTE_BLOCK_PXN | PTE_BLOCK_UXN
553 }, {
554 /* I/O */
555 .virt = 0x1300000000,
556 .phys = 0x1300000000,
557 .size = SZ_1G,
558 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
559 PTE_BLOCK_NON_SHARE |
560 PTE_BLOCK_PXN | PTE_BLOCK_UXN
561 }, {
562 /* I/O */
563 .virt = 0x2280000000,
564 .phys = 0x2280000000,
565 .size = SZ_1G,
566 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
567 PTE_BLOCK_NON_SHARE |
568 PTE_BLOCK_PXN | PTE_BLOCK_UXN
569 }, {
570 /* I/O */
571 .virt = 0x2340000000,
572 .phys = 0x2340000000,
573 .size = SZ_1G,
574 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
575 PTE_BLOCK_NON_SHARE |
576 PTE_BLOCK_PXN | PTE_BLOCK_UXN
577 }, {
578 /* I/O */
579 .virt = 0x2380000000,
580 .phys = 0x2380000000,
581 .size = SZ_1G,
582 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
583 PTE_BLOCK_NON_SHARE |
584 PTE_BLOCK_PXN | PTE_BLOCK_UXN
585 }, {
586 /* I/O */
Janne Grunauefc0df02023-12-01 08:12:33 +0100[diff] [blame]587 .virt = 0x2400000000,
588 .phys = 0x2400000000,
589 .size = SZ_1G,
590 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
591 PTE_BLOCK_NON_SHARE |
592 PTE_BLOCK_PXN | PTE_BLOCK_UXN
593 }, {
594 /* I/O */
595 .virt = 0x2480000000,
596 .phys = 0x2480000000,
597 .size = SZ_1G,
598 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
599 PTE_BLOCK_NON_SHARE |
600 PTE_BLOCK_PXN | PTE_BLOCK_UXN
601 }, {
602 /* I/O */
Janne Grunau19e1c482023-09-06 23:50:34 +0200[diff] [blame]603 .virt = 0x2580000000,
604 .phys = 0x2580000000,
605 .size = SZ_512M,
606 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
607 PTE_BLOCK_NON_SHARE |
608 PTE_BLOCK_PXN | PTE_BLOCK_UXN
609 }, {
610 /* PCIE */
611 .virt = 0x25a0000000,
612 .phys = 0x25a0000000,
613 .size = SZ_512M,
614 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
615 PTE_BLOCK_INNER_SHARE |
616 PTE_BLOCK_PXN | PTE_BLOCK_UXN
617 }, {
618 /* PCIE */
619 .virt = 0x25c0000000,
620 .phys = 0x25c0000000,
621 .size = SZ_1G,
622 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
623 PTE_BLOCK_INNER_SHARE |
624 PTE_BLOCK_PXN | PTE_BLOCK_UXN
625 }, {
626 /* I/O */
627 .virt = 0x2700000000,
628 .phys = 0x2700000000,
629 .size = SZ_1G,
630 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
631 PTE_BLOCK_NON_SHARE |
632 PTE_BLOCK_PXN | PTE_BLOCK_UXN
633 }, {
634 /* I/O */
635 .virt = 0x2b00000000,
636 .phys = 0x2b00000000,
637 .size = SZ_1G,
638 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
639 PTE_BLOCK_NON_SHARE |
640 PTE_BLOCK_PXN | PTE_BLOCK_UXN
641 }, {
642 /* I/O */
643 .virt = 0x2f00000000,
644 .phys = 0x2f00000000,
645 .size = SZ_1G,
646 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
647 PTE_BLOCK_NON_SHARE |
648 PTE_BLOCK_PXN | PTE_BLOCK_UXN
649 }, {
650 /* I/O */
651 .virt = 0x3300000000,
652 .phys = 0x3300000000,
653 .size = SZ_1G,
654 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
655 PTE_BLOCK_NON_SHARE |
656 PTE_BLOCK_PXN | PTE_BLOCK_UXN
657 }, {
658 /* RAM */
659 .virt = 0x10000000000,
660 .phys = 0x10000000000,
661 .size = 16UL * SZ_1G,
662 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
663 PTE_BLOCK_INNER_SHARE
664 }, {
665 /* Framebuffer */
666 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
667 PTE_BLOCK_INNER_SHARE |
668 PTE_BLOCK_PXN | PTE_BLOCK_UXN
669 }, {
670 /* List terminator */
671 0,
672 }
673};
674
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]675struct mm_region *mem_map;
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]676
677int board_init(void)
678{
679 return 0;
680}
681
682int dram_init(void)
683{
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]684 return fdtdec_setup_mem_size_base();
685}
686
687int dram_init_banksize(void)
688{
689 return fdtdec_setup_memory_banksize();
690}
691
692extern long fw_dtb_pointer;
693
694void *board_fdt_blob_setup(int *err)
695{
696 /* Return DTB pointer passed by m1n1 */
697 *err = 0;
698 return (void *)fw_dtb_pointer;
699}
700
701void build_mem_map(void)
702{
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]703 ofnode node;
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]704 fdt_addr_t base;
705 fdt_size_t size;
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]706 int i;
707
Janne Grunau430ff522022-07-01 00:06:17 +0200[diff] [blame]708 if (of_machine_is_compatible("apple,t8103") ||
709 of_machine_is_compatible("apple,t8112"))
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]710 mem_map = t8103_mem_map;
Mark Kettenis1b350702023-05-02 21:30:40 +0200[diff] [blame]711 else if (of_machine_is_compatible("apple,t6000") ||
712 of_machine_is_compatible("apple,t6001"))
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]713 mem_map = t6000_mem_map;
Janne Grunaudc174322022-03-29 13:29:35 +0200[diff] [blame]714 else if (of_machine_is_compatible("apple,t6002"))
715 mem_map = t6002_mem_map;
Mark Kettenis1b350702023-05-02 21:30:40 +0200[diff] [blame]716 else if (of_machine_is_compatible("apple,t6020") ||
717 of_machine_is_compatible("apple,t6021"))
718 mem_map = t6020_mem_map;
Janne Grunau19e1c482023-09-06 23:50:34 +0200[diff] [blame]719 else if (of_machine_is_compatible("apple,t6022"))
720 mem_map = t6022_mem_map;
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]721 else
722 panic("Unsupported SoC\n");
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]723
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]724 /* Find list terminator. */
725 for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
726 ;
727
728 /* Align RAM mapping to page boundaries */
729 base = gd->bd->bi_dram[0].start;
730 size = gd->bd->bi_dram[0].size;
731 size += (base - ALIGN_DOWN(base, SZ_4K));
732 base = ALIGN_DOWN(base, SZ_4K);
733 size = ALIGN(size, SZ_4K);
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]734
735 /* Update RAM mapping */
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]736 mem_map[i - 2].virt = base;
737 mem_map[i - 2].phys = base;
738 mem_map[i - 2].size = size;
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]739
740 node = ofnode_path("/chosen/framebuffer");
741 if (!ofnode_valid(node))
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]742 return;
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]743
744 base = ofnode_get_addr_size(node, "reg", &size);
745 if (base == FDT_ADDR_T_NONE)
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]746 return;
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]747
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]748 /* Align framebuffer mapping to page boundaries */
749 size += (base - ALIGN_DOWN(base, SZ_4K));
750 base = ALIGN_DOWN(base, SZ_4K);
751 size = ALIGN(size, SZ_4K);
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]752
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]753 /* Add framebuffer mapping */
754 mem_map[i - 1].virt = base;
755 mem_map[i - 1].phys = base;
756 mem_map[i - 1].size = size;
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]757}
758
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]759void enable_caches(void)
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]760{
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]761 build_mem_map();
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]762
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]763 icache_enable();
764 dcache_enable();
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]765}
766
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]767u64 get_page_table_size(void)
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]768{
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]769 return SZ_256K;
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]770}
Janne Grunau3a216712022-02-19 14:05:19 +0100[diff] [blame]771
Mark Kettenis74ec0482022-03-21 22:41:18 +0100[diff] [blame]772#define KERNEL_COMP_SIZE SZ_128M
773
Janne Grunau3a216712022-02-19 14:05:19 +0100[diff] [blame]774int board_late_init(void)
775{
Janne Grunau3a216712022-02-19 14:05:19 +0100[diff] [blame]776 u32 status = 0;
777
Janne Grunau3a216712022-02-19 14:05:19 +0100[diff] [blame]778 /* somewhat based on the Linux Kernel boot requirements:
779 * align by 2M and maximal FDT size 2M
780 */
Sughosh Ganu291bf9c2024-08-26 17:29:18 +0530[diff] [blame]781 status |= env_set_hex("loadaddr", lmb_alloc(SZ_1G, SZ_2M));
782 status |= env_set_hex("fdt_addr_r", lmb_alloc(SZ_2M, SZ_2M));
783 status |= env_set_hex("kernel_addr_r", lmb_alloc(SZ_128M, SZ_2M));
784 status |= env_set_hex("ramdisk_addr_r", lmb_alloc(SZ_1G, SZ_2M));
Mark Kettenis74ec0482022-03-21 22:41:18 +0100[diff] [blame]785 status |= env_set_hex("kernel_comp_addr_r",
Sughosh Ganu291bf9c2024-08-26 17:29:18 +0530[diff] [blame]786 lmb_alloc(KERNEL_COMP_SIZE, SZ_2M));
Mark Kettenis74ec0482022-03-21 22:41:18 +0100[diff] [blame]787 status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE);
Sughosh Ganu291bf9c2024-08-26 17:29:18 +0530[diff] [blame]788 status |= env_set_hex("scriptaddr", lmb_alloc(SZ_4M, SZ_2M));
789 status |= env_set_hex("pxefile_addr_r", lmb_alloc(SZ_4M, SZ_2M));
Janne Grunau3a216712022-02-19 14:05:19 +0100[diff] [blame]790
791 if (status)
792 log_warning("late_init: Failed to set run time variables\n");
793
794 return 0;
795}
Mark Kettenisdfacafb2022-04-19 21:20:31 +0200[diff] [blame]796
797int ft_board_setup(void *blob, struct bd_info *bd)
798{
799 struct udevice *dev;
800 const char *stdoutname;
801 int node, ret;
802
803 /*
804 * Modify the "stdout-path" property under "/chosen" to point
805 * at "/chosen/framebuffer if a keyboard is available and
806 * we're not running under the m1n1 hypervisor.
807 * Developers can override this behaviour by dropping
808 * "vidconsole" from the "stdout" environment variable.
809 */
810
811 /* EL1 means we're running under the m1n1 hypervisor. */
812 if (current_el() == 1)
813 return 0;
814
815 ret = uclass_find_device(UCLASS_KEYBOARD, 0, &dev);
816 if (ret < 0)
817 return 0;
818
819 stdoutname = env_get("stdout");
820 if (!stdoutname || !strstr(stdoutname, "vidconsole"))
821 return 0;
822
823 /* Make sure we actually have a framebuffer. */
824 node = fdt_path_offset(blob, "/chosen/framebuffer");
825 if (node < 0 || !fdtdec_get_is_enabled(blob, node))
826 return 0;
827
828 node = fdt_path_offset(blob, "/chosen");
829 if (node < 0)
830 return 0;
831 fdt_setprop_string(blob, node, "stdout-path", "/chosen/framebuffer");
832
833 return 0;
834}