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Masahiro Yamadacc85b7b2015-07-26 02:46:26 +09001#
2# Multifunction miscellaneous devices
3#
4
5menu "Multifunction device drivers"
6
Thomas Choub1ed6862015-10-07 20:20:51 +08007config MISC
8 bool "Enable Driver Model for Misc drivers"
9 depends on DM
10 help
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
14 access the device.
15
Simon Glass605931c2018-11-18 08:14:27 -070016config SPL_MISC
17 bool "Enable Driver Model for Misc drivers in SPL"
18 depends on SPL_DM
Sean Anderson63c318f2022-04-22 16:11:37 -040019 default MISC
Simon Glass605931c2018-11-18 08:14:27 -070020 help
21 Enable driver model for miscellaneous devices. This class is
22 used only for those do not fit other more general classes. A
23 set of generic read, write and ioctl methods may be used to
24 access the device.
25
26config TPL_MISC
27 bool "Enable Driver Model for Misc drivers in TPL"
28 depends on TPL_DM
Sean Anderson63c318f2022-04-22 16:11:37 -040029 default MISC
30 help
31 Enable driver model for miscellaneous devices. This class is
32 used only for those do not fit other more general classes. A
33 set of generic read, write and ioctl methods may be used to
34 access the device.
35
36config VPL_MISC
37 bool "Enable Driver Model for Misc drivers in VPL"
38 depends on VPL_DM
39 default MISC
Simon Glass605931c2018-11-18 08:14:27 -070040 help
41 Enable driver model for miscellaneous devices. This class is
42 used only for those do not fit other more general classes. A
43 set of generic read, write and ioctl methods may be used to
44 access the device.
45
Sean Anderson77c66292022-05-05 13:11:39 -040046config NVMEM
47 bool "NVMEM support"
48 help
49 This adds support for a common interface to different types of
50 non-volatile memory. Consumers can use nvmem-cells properties to look
51 up hardware configuration data such as MAC addresses and calibration
52 settings.
53
54config SPL_NVMEM
55 bool "NVMEM support in SPL"
56 help
57 This adds support for a common interface to different types of
58 non-volatile memory. Consumers can use nvmem-cells properties to look
59 up hardware configuration data such as MAC addresses and calibration
60 settings.
61
Thomas Chou36b9c9a2015-10-14 08:43:31 +080062config ALTERA_SYSID
63 bool "Altera Sysid support"
64 depends on MISC
65 help
66 Select this to enable a sysid for Altera devices. Please find
67 details on the "Embedded Peripherals IP User Guide" of Altera.
68
Marek Behúnef2b6b12017-06-09 19:28:44 +020069config ATSHA204A
70 bool "Support for Atmel ATSHA204A module"
Pali Rohár2e269302022-04-12 11:20:44 +020071 select BITREVERSE
Marek Behúnef2b6b12017-06-09 19:28:44 +020072 depends on MISC
73 help
74 Enable support for I2C connected Atmel's ATSHA204A
75 CryptoAuthentication module found for example on the Turris Omnia
76 board.
77
Tim Harveyb8204602022-03-07 16:24:04 -080078config GATEWORKS_SC
79 bool "Gateworks System Controller Support"
80 depends on MISC
81 help
82 Enable access for the Gateworks System Controller used on Gateworks
83 boards to provide a boot watchdog, power control, temperature monitor,
84 voltage ADCs, and EEPROM.
85
Philipp Tomsichfcc1d632017-05-05 19:21:38 +020086config ROCKCHIP_EFUSE
87 bool "Rockchip e-fuse support"
88 depends on MISC
89 help
90 Enable (read-only) access for the e-fuse block found in Rockchip
91 SoCs: accesses can either be made using byte addressing and a length
92 or through child-nodes that are generated based on the e-fuse map
93 retrieved from the DTS.
94
95 This driver currently supports the RK3399 only, but can easily be
96 extended (by porting the read function from the Linux kernel sources)
97 to support other recent Rockchip devices.
98
Finley Xiao20d52a02019-09-25 17:57:49 +020099config ROCKCHIP_OTP
100 bool "Rockchip OTP Support"
101 depends on MISC
102 help
103 Enable (read-only) access for the one-time-programmable memory block
104 found in Rockchip SoCs: accesses can either be made using byte
105 addressing and a length or through child-nodes that are generated
106 based on the e-fuse map retrieved from the DTS.
107
Pragnesh Patel6e9661f2020-05-29 11:33:21 +0530108config SIFIVE_OTP
109 bool "SiFive eMemory OTP driver"
110 depends on MISC
111 help
112 Enable support for reading and writing the eMemory OTP on the
113 SiFive SoCs.
114
Liviu Dudau688db7f2018-09-28 13:43:31 +0100115config VEXPRESS_CONFIG
116 bool "Enable support for Arm Versatile Express config bus"
117 depends on MISC
118 help
119 If you say Y here, you will get support for accessing the
120 configuration bus on the Arm Versatile Express boards via
121 a sysreg driver.
122
Simon Glass5b79bb22015-02-13 12:20:47 -0700123config CMD_CROS_EC
124 bool "Enable crosec command"
125 depends on CROS_EC
126 help
127 Enable command-line access to the Chrome OS EC (Embedded
128 Controller). This provides the 'crosec' command which has
129 a number of sub-commands for performing EC tasks such as
130 updating its flash, accessing a small saved context area
131 and talking to the I2C bus behind the EC (if there is one).
132
133config CROS_EC
134 bool "Enable Chrome OS EC"
135 help
136 Enable access to the Chrome OS EC. This is a separate
137 microcontroller typically available on a SPI bus on Chromebooks. It
138 provides access to the keyboard, some internal storage and may
139 control access to the battery and main PMIC depending on the
140 device. You can use the 'crosec' command to access it.
141
Simon Glass605931c2018-11-18 08:14:27 -0700142config SPL_CROS_EC
143 bool "Enable Chrome OS EC in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400144 depends on SPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700145 help
146 Enable access to the Chrome OS EC in SPL. This is a separate
147 microcontroller typically available on a SPI bus on Chromebooks. It
148 provides access to the keyboard, some internal storage and may
149 control access to the battery and main PMIC depending on the
150 device. You can use the 'crosec' command to access it.
151
152config TPL_CROS_EC
153 bool "Enable Chrome OS EC in TPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400154 depends on TPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700155 help
156 Enable access to the Chrome OS EC in TPL. This is a separate
157 microcontroller typically available on a SPI bus on Chromebooks. It
158 provides access to the keyboard, some internal storage and may
159 control access to the battery and main PMIC depending on the
160 device. You can use the 'crosec' command to access it.
161
Simon Glasse7ca7da2022-04-30 00:56:53 -0600162config VPL_CROS_EC
163 bool "Enable Chrome OS EC in VPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400164 depends on VPL_MISC
Simon Glasse7ca7da2022-04-30 00:56:53 -0600165 help
166 Enable access to the Chrome OS EC in VPL. This is a separate
167 microcontroller typically available on a SPI bus on Chromebooks. It
168 provides access to the keyboard, some internal storage and may
169 control access to the battery and main PMIC depending on the
170 device. You can use the 'crosec' command to access it.
171
Simon Glass5b79bb22015-02-13 12:20:47 -0700172config CROS_EC_I2C
173 bool "Enable Chrome OS EC I2C driver"
174 depends on CROS_EC
175 help
176 Enable I2C access to the Chrome OS EC. This is used on older
177 ARM Chromebooks such as snow and spring before the standard bus
178 changed to SPI. The EC will accept commands across the I2C using
179 a special message protocol, and provide responses.
180
181config CROS_EC_LPC
182 bool "Enable Chrome OS EC LPC driver"
183 depends on CROS_EC
184 help
185 Enable I2C access to the Chrome OS EC. This is used on x86
186 Chromebooks such as link and falco. The keyboard is provided
187 through a legacy port interface, so on x86 machines the main
188 function of the EC is power and thermal management.
189
Simon Glass605931c2018-11-18 08:14:27 -0700190config SPL_CROS_EC_LPC
191 bool "Enable Chrome OS EC LPC driver in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400192 depends on CROS_EC && SPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700193 help
194 Enable I2C access to the Chrome OS EC. This is used on x86
195 Chromebooks such as link and falco. The keyboard is provided
196 through a legacy port interface, so on x86 machines the main
197 function of the EC is power and thermal management.
198
199config TPL_CROS_EC_LPC
200 bool "Enable Chrome OS EC LPC driver in TPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400201 depends on CROS_EC && TPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700202 help
203 Enable I2C access to the Chrome OS EC. This is used on x86
204 Chromebooks such as link and falco. The keyboard is provided
205 through a legacy port interface, so on x86 machines the main
206 function of the EC is power and thermal management.
207
Simon Glasse7ca7da2022-04-30 00:56:53 -0600208config VPL_CROS_EC_LPC
209 bool "Enable Chrome OS EC LPC driver in VPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400210 depends on CROS_EC && VPL_MISC
Simon Glasse7ca7da2022-04-30 00:56:53 -0600211 help
212 Enable I2C access to the Chrome OS EC. This is used on x86
213 Chromebooks such as link and falco. The keyboard is provided
214 through a legacy port interface, so on x86 machines the main
215 function of the EC is power and thermal management.
216
Simon Glassc6e06692015-03-26 09:29:40 -0600217config CROS_EC_SANDBOX
218 bool "Enable Chrome OS EC sandbox driver"
219 depends on CROS_EC && SANDBOX
220 help
221 Enable a sandbox emulation of the Chrome OS EC. This supports
222 keyboard (use the -l flag to enable the LCD), verified boot context,
223 EC flash read/write/erase support and a few other things. It is
224 enough to perform a Chrome OS verified boot on sandbox.
225
Simon Glass605931c2018-11-18 08:14:27 -0700226config SPL_CROS_EC_SANDBOX
227 bool "Enable Chrome OS EC sandbox driver in SPL"
228 depends on SPL_CROS_EC && SANDBOX
229 help
230 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
231 keyboard (use the -l flag to enable the LCD), verified boot context,
232 EC flash read/write/erase support and a few other things. It is
233 enough to perform a Chrome OS verified boot on sandbox.
234
235config TPL_CROS_EC_SANDBOX
236 bool "Enable Chrome OS EC sandbox driver in TPL"
237 depends on TPL_CROS_EC && SANDBOX
238 help
239 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
240 keyboard (use the -l flag to enable the LCD), verified boot context,
241 EC flash read/write/erase support and a few other things. It is
242 enough to perform a Chrome OS verified boot on sandbox.
243
Simon Glasse7ca7da2022-04-30 00:56:53 -0600244config VPL_CROS_EC_SANDBOX
245 bool "Enable Chrome OS EC sandbox driver in VPL"
246 depends on VPL_CROS_EC && SANDBOX
247 help
248 Enable a sandbox emulation of the Chrome OS EC in VPL. This supports
249 keyboard (use the -l flag to enable the LCD), verified boot context,
250 EC flash read/write/erase support and a few other things. It is
251 enough to perform a Chrome OS verified boot on sandbox.
252
Simon Glass5b79bb22015-02-13 12:20:47 -0700253config CROS_EC_SPI
254 bool "Enable Chrome OS EC SPI driver"
255 depends on CROS_EC
256 help
257 Enable SPI access to the Chrome OS EC. This is used on newer
258 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
259 provides a faster and more robust interface than I2C but the bugs
260 are less interesting.
261
Simon Glass58ed3222017-05-17 03:25:02 -0600262config DS4510
263 bool "Enable support for DS4510 CPU supervisor"
264 help
265 Enable support for the Maxim DS4510 CPU supervisor. It has an
266 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
267 and a configurable timer for the supervisor function. The device is
268 connected over I2C.
269
Peng Fanfb6166a2015-08-26 15:41:33 +0800270config FSL_SEC_MON
gaurav rana9aaea442015-02-27 09:44:22 +0530271 bool "Enable FSL SEC_MON Driver"
272 help
273 Freescale Security Monitor block is responsible for monitoring
274 system states.
275 Security Monitor can be transitioned on any security failures,
276 like software violations or hardware security violations.
Stefan Roese04b22752015-03-12 11:22:46 +0100277
Tom Rini0b58c2e2022-06-16 14:04:39 -0400278choice
279 prompt "Security monitor interaction endianess"
280 depends on FSL_SEC_MON
281 default SYS_FSL_SEC_MON_BE if PPC
282 default SYS_FSL_SEC_MON_LE
283
284config SYS_FSL_SEC_MON_LE
285 bool "Security monitor interactions are little endian"
286
287config SYS_FSL_SEC_MON_BE
288 bool "Security monitor interactions are big endian"
289
290endchoice
291
Simon Glassff418d92019-12-06 21:41:58 -0700292config IRQ
Wasim Khan55c9b9c2021-03-08 16:48:13 +0100293 bool "Interrupt controller"
Simon Glassff418d92019-12-06 21:41:58 -0700294 help
Wasim Khan55c9b9c2021-03-08 16:48:13 +0100295 This enables support for interrupt controllers, including ITSS.
Simon Glassff418d92019-12-06 21:41:58 -0700296 Some devices have extra features, such as Apollo Lake. The
297 device has its own uclass since there are several operations
298 involved.
299
Paul Burton738d8a82018-12-16 19:25:19 -0300300config JZ4780_EFUSE
301 bool "Ingenic JZ4780 eFUSE support"
302 depends on ARCH_JZ47XX
303 help
304 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
305
Sean Anderson6b39d352022-04-22 14:34:18 -0400306config LS2_SFP
307 bool "Layerscape Security Fuse Processor"
308 depends on FSL_LSCH2 || ARCH_LS1021A
309 depends on MISC
310 imply DM_REGULATOR
311 help
312 This adds support for the Security Fuse Processor found on Layerscape
313 SoCs. It contains various fuses related to secure boot, including the
314 Super Root Key hash, One-Time-Programmable Master Key, Debug
315 Challenge/Response values, and others. Fuses are numbered according
316 to their four-byte offset from the start of the bank.
317
318 If you don't need to read/program fuses, say 'n'.
319
Peng Fane1872252015-08-27 14:49:05 +0800320config MXC_OCOTP
321 bool "Enable MXC OCOTP Driver"
Peng Fanc45a81a2019-07-22 01:24:55 +0000322 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
Marcel Ziswilerf2213142019-03-25 17:24:57 +0100323 default y
Peng Fane1872252015-08-27 14:49:05 +0800324 help
325 If you say Y here, you will get support for the One Time
326 Programmable memory pages that are stored on the some
327 Freescale i.MX processors.
328
Jim Liucce4eed2022-06-24 16:24:37 +0800329config NPCM_HOST
330 bool "Enable support espi or LPC for Host"
331 depends on REGMAP && SYSCON
332 help
333 Enable NPCM BMC espi or LPC support for Host reading and writing.
334
Michael Scott92676142021-09-25 19:49:28 +0300335config SPL_MXC_OCOTP
336 bool "Enable MXC OCOTP driver in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400337 depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
Michael Scott92676142021-09-25 19:49:28 +0300338 default y
339 help
340 If you say Y here, you will get support for the One Time
341 Programmable memory pages, that are stored on some
342 Freescale i.MX processors, in SPL.
343
Jim Liufab2eff2022-06-07 16:33:54 +0800344config NPCM_OTP
345 bool "Nnvoton NPCM BMC On-Chip OTP Memory Support"
346 depends on (ARM && ARCH_NPCM)
347 default n
348 help
349 Support NPCM BMC OTP memory (fuse).
350 To compile this driver as a module, choose M here: the module
351 will be called npcm_otp.
352
Ye Lic408ed32022-07-26 16:40:49 +0800353config IMX_SENTINEL
354 bool "Enable i.MX Sentinel MU driver and API"
355 depends on MISC && (ARCH_IMX9 || ARCH_IMX8ULP)
356 help
357 If you say Y here to enable Message Unit driver to work with
358 Sentinel core on some NXP i.MX processors.
359
Stefan Roese4a269f22016-07-19 07:45:46 +0200360config NUVOTON_NCT6102D
361 bool "Enable Nuvoton NCT6102D Super I/O driver"
362 help
363 If you say Y here, you will get support for the Nuvoton
364 NCT6102D Super I/O driver. This can be used to enable or
365 disable the legacy UART, the watchdog or other devices
366 in the Nuvoton Super IO chips on X86 platforms.
367
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700368config P2SB
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200369 bool "Intel Primary to Sideband Bridge"
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700370 depends on X86 || SANDBOX
371 help
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200372 This enables support for the Intel Primary to Sideband Bridge,
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700373 abbreviated to P2SB. The P2SB is used to access various peripherals
374 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
375 space. The space is segmented into different channels and peripherals
376 are accessed by device-specific means within those channels. Devices
377 should be added in the device tree as subnodes of the P2SB. A
378 Peripheral Channel Register? (PCR) API is provided to access those
379 devices - see pcr_readl(), etc.
380
381config SPL_P2SB
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200382 bool "Intel Primary to Sideband Bridge in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400383 depends on SPL_MISC && (X86 || SANDBOX)
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700384 help
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200385 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700386 through memory-mapped I/O in a large chunk of PCI space. The space is
387 segmented into different channels and peripherals are accessed by
388 device-specific means within those channels. Devices should be added
389 in the device tree as subnodes of the p2sb.
390
391config TPL_P2SB
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200392 bool "Intel Primary to Sideband Bridge in TPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400393 depends on TPL_MISC && (X86 || SANDBOX)
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700394 help
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200395 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700396 through memory-mapped I/O in a large chunk of PCI space. The space is
397 segmented into different channels and peripherals are accessed by
398 device-specific means within those channels. Devices should be added
399 in the device tree as subnodes of the p2sb.
400
Simon Glassc9795172016-01-21 19:43:31 -0700401config PWRSEQ
402 bool "Enable power-sequencing drivers"
403 depends on DM
404 help
405 Power-sequencing drivers provide support for controlling power for
406 devices. They are typically referenced by a phandle from another
407 device. When the device is started up, its power sequence can be
408 initiated.
409
410config SPL_PWRSEQ
411 bool "Enable power-sequencing drivers for SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400412 depends on SPL_MISC && PWRSEQ
Simon Glassc9795172016-01-21 19:43:31 -0700413 help
414 Power-sequencing drivers provide support for controlling power for
415 devices. They are typically referenced by a phandle from another
416 device. When the device is started up, its power sequence can be
417 initiated.
418
Stefan Roese04b22752015-03-12 11:22:46 +0100419config PCA9551_LED
420 bool "Enable PCA9551 LED driver"
421 help
422 Enable driver for PCA9551 LED controller. This controller
423 is connected via I2C. So I2C needs to be enabled.
424
425config PCA9551_I2C_ADDR
426 hex "I2C address of PCA9551 LED controller"
427 depends on PCA9551_LED
428 default 0x60
429 help
430 The I2C address of the PCA9551 LED controller.
Simon Glass14000862015-06-23 15:39:13 -0600431
Patrick Delaunay0c4656b2018-05-17 15:24:06 +0200432config STM32MP_FUSE
433 bool "Enable STM32MP fuse wrapper providing the fuse API"
434 depends on ARCH_STM32MP && MISC
435 default y if CMD_FUSE
436 help
437 If you say Y here, you will get support for the fuse API (OTP)
438 for STM32MP architecture.
439 This API is needed for CMD_FUSE.
440
Christophe Kerello275f7062017-09-13 18:00:08 +0200441config STM32_RCC
442 bool "Enable RCC driver for the STM32 SoC's family"
Trevor Woerner2bcc1ed2020-05-06 08:02:42 -0400443 depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
Christophe Kerello275f7062017-09-13 18:00:08 +0200444 help
445 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
446 block) is responsible of the management of the clock and reset
447 generation.
448 This driver is similar to an MFD driver in the Linux kernel.
449
Stephen Warrenf6417002016-09-13 10:45:57 -0600450config TEGRA_CAR
451 bool "Enable support for the Tegra CAR driver"
452 depends on TEGRA_NO_BPMP
453 help
454 The Tegra CAR (Clock and Reset Controller) is a HW module that
455 controls almost all clocks and resets in a Tegra SoC.
456
Stephen Warrena2148922016-08-08 09:41:34 -0600457config TEGRA186_BPMP
458 bool "Enable support for the Tegra186 BPMP driver"
459 depends on TEGRA186
460 help
461 The Tegra BPMP (Boot and Power Management Processor) is a separate
462 auxiliary CPU embedded into Tegra to perform power management work,
463 and controls related features such as clocks, resets, power domains,
464 PMIC I2C bus, etc. This driver provides the core low-level
465 communication path by which feature-specific drivers (such as clock)
466 can make requests to the BPMP. This driver is similar to an MFD
467 driver in the Linux kernel.
468
Simon Glass4bf89722020-12-23 08:11:18 -0700469config TEST_DRV
470 bool "Enable support for test drivers"
471 default y if SANDBOX
472 help
473 This enables drivers and uclasses that provides a way of testing the
474 operations of memory allocation and driver/uclass methods in driver
475 model. This should only be enabled for testing as it is not useful for
476 anything else.
477
Marek Vasut16637b42022-04-10 06:27:14 +0200478config USB_HUB_USB251XB
479 tristate "USB251XB Hub Controller Configuration Driver"
480 depends on I2C
481 help
482 This option enables support for configuration via SMBus of the
483 Microchip USB251x/xBi USB 2.0 Hub Controller series. Configuration
484 parameters may be set in devicetree or platform data.
485 Say Y or M here if you need to configure such a device via SMBus.
486
Adam Fordc8cdce72018-08-06 14:26:50 -0500487config TWL4030_LED
488 bool "Enable TWL4030 LED controller"
489 help
490 Enable this to add support for the TWL4030 LED controller.
491
Stefan Roeseba019ed2016-01-19 14:05:10 +0100492config WINBOND_W83627
493 bool "Enable Winbond Super I/O driver"
494 help
495 If you say Y here, you will get support for the Winbond
496 W83627 Super I/O driver. This can be used to enable the
497 legacy UART or other devices in the Winbond Super IO chips
498 on X86 platforms.
499
Miao Yan4fcd7f22016-05-22 19:37:14 -0700500config QFW
501 bool
502 help
Asherah Connor4ffa95d2021-03-19 18:21:40 +1100503 Hidden option to enable QEMU fw_cfg interface and uclass. This will
504 be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
505
506config QFW_PIO
507 bool
508 depends on QFW
509 help
510 Hidden option to enable PIO QEMU fw_cfg interface. This will be
511 selected by the appropriate QEMU board.
Miao Yan4fcd7f22016-05-22 19:37:14 -0700512
Asherah Connorf0c0e542021-03-19 18:21:42 +1100513config QFW_MMIO
514 bool
515 depends on QFW
516 help
517 Hidden option to enable MMIO QEMU fw_cfg interface. This will be
518 selected by the appropriate QEMU board.
519
mario.six@gdsys.cc7559ac42016-06-22 15:14:16 +0200520config I2C_EEPROM
521 bool "Enable driver for generic I2C-attached EEPROMs"
522 depends on MISC
523 help
524 Enable a generic driver for EEPROMs attached via I2C.
Adam Ford5664f832017-08-13 09:00:28 -0500525
Wenyou Yangf791d562017-09-06 13:08:14 +0800526
527config SPL_I2C_EEPROM
528 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400529 depends on SPL_MISC
Wenyou Yangf791d562017-09-06 13:08:14 +0800530 help
531 This option is an SPL-variant of the I2C_EEPROM option.
532 See the help of I2C_EEPROM for details.
533
Adam Ford5664f832017-08-13 09:00:28 -0500534config SYS_I2C_EEPROM_ADDR
535 hex "Chip address of the EEPROM device"
Tom Rinifaed5672021-08-17 17:59:45 -0400536 depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
Adam Ford5664f832017-08-13 09:00:28 -0500537 default 0
Adam Ford5664f832017-08-13 09:00:28 -0500538
Tom Rinifaed5672021-08-17 17:59:45 -0400539if I2C_EEPROM
Adam Ford5664f832017-08-13 09:00:28 -0500540
541config SYS_I2C_EEPROM_ADDR_OVERFLOW
542 hex "EEPROM Address Overflow"
Tom Rinif0599552021-12-11 14:55:47 -0500543 default 0x0
Adam Ford5664f832017-08-13 09:00:28 -0500544 help
545 EEPROM chips that implement "address overflow" are ones
546 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
547 address and the extra bits end up in the "chip address" bit
548 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
549 byte chips.
550
551endif
552
Mario Six7f504a02018-04-27 14:53:33 +0200553config GDSYS_RXAUI_CTRL
554 bool "Enable gdsys RXAUI control driver"
555 depends on MISC
556 help
557 Support gdsys FPGA's RXAUI control.
Mario Six0cafb652018-07-31 14:24:15 +0200558
559config GDSYS_IOEP
560 bool "Enable gdsys IOEP driver"
561 depends on MISC
562 help
563 Support gdsys FPGA's IO endpoint driver.
Mario Six7fdcf282018-08-06 10:23:46 +0200564
565config MPC83XX_SERDES
566 bool "Enable MPC83xx serdes driver"
567 depends on MISC
568 help
569 Support for serdes found on MPC83xx SoCs.
570
Tien Fong Chee5ca878b2018-07-06 16:28:03 +0800571config FS_LOADER
572 bool "Enable loader driver for file system"
573 help
574 This is file system generic loader which can be used to load
575 the file image from the storage into target such as memory.
576
577 The consumer driver would then use this loader to program whatever,
578 ie. the FPGA device.
579
Keerthyfe8f6092022-01-27 13:16:53 +0100580config SPL_FS_LOADER
581 bool "Enable loader driver for file system"
Tom Rini0f311f22022-05-10 12:51:47 -0400582 depends on SPL
Keerthyfe8f6092022-01-27 13:16:53 +0100583 help
584 This is file system generic loader which can be used to load
585 the file image from the storage into target such as memory.
586
587 The consumer driver would then use this loader to program whatever,
588 ie. the FPGA device.
589
Mario Six8862f452018-10-04 09:00:54 +0200590config GDSYS_SOC
591 bool "Enable gdsys SOC driver"
592 depends on MISC
593 help
594 Support for gdsys IHS SOC, a simple bus associated with each gdsys
595 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
596 register maps are contained within the FPGA's register map.
597
Mario Six1a9d43f2018-10-04 09:00:55 +0200598config IHS_FPGA
599 bool "Enable IHS FPGA driver"
600 depends on MISC
601 help
602 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
603 gdsys devices, which supply the majority of the functionality offered
604 by the devices. This driver supports both CON and CPU variants of the
605 devices, depending on the device tree entry.
Tero Kristof81f4cd2020-02-14 11:18:15 +0200606config ESM_K3
607 bool "Enable K3 ESM driver"
608 depends on ARCH_K3
609 help
610 Support ESM (Error Signaling Module) on TI K3 SoCs.
Mario Six1a9d43f2018-10-04 09:00:55 +0200611
Eugen Hristev3bd56102019-10-09 09:23:39 +0000612config MICROCHIP_FLEXCOM
613 bool "Enable Microchip Flexcom driver"
614 depends on MISC
615 help
616 The Atmel Flexcom is just a wrapper which embeds a SPI controller,
617 an I2C controller and an USART.
618 Only one function can be used at a time and is chosen at boot time
619 according to the device tree.
620
Tero Kristo887dde52019-10-24 15:00:46 +0530621config K3_AVS0
622 depends on ARCH_K3 && SPL_DM_REGULATOR
623 bool "AVS class 0 support for K3 devices"
624 help
625 K3 devices have the optimized voltage values for the main voltage
626 domains stored in efuse within the VTM IP. This driver reads the
627 optimized voltage from the efuse, so that it can be programmed
628 to the PMIC on board.
629
Tero Kristo1444e112020-02-14 11:18:16 +0200630config ESM_PMIC
631 bool "Enable PMIC ESM driver"
632 depends on DM_PMIC
633 help
634 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
635 typically to reboot the board in error condition.
636
Tom Rini05b419e2021-12-11 14:55:49 -0500637config FSL_IFC
638 bool
639
Michael Walle2184cc62022-02-25 18:06:24 +0530640config SL28CPLD
641 bool "Enable Kontron sl28cpld multi-function driver"
642 depends on DM_I2C
643 help
644 Support for the Kontron sl28cpld management controller. This is
645 the base driver which provides common access methods for the
646 sub-drivers.
647
Masahiro Yamadacc85b7b2015-07-26 02:46:26 +0900648endmenu