blob: beb8f1ae9a92f1724446d9f2cccda0a043bfe9c6 [file] [log] [blame]
Vikas Manocha33913c52014-11-18 10:42:22 -08001/*
Patrice Chotardcc551162017-10-23 09:53:59 +02002 * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
3 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
Vikas Manocha33913c52014-11-18 10:42:22 -08004 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef __CONFIG_STV0991_H
9#define __CONFIG_STV0991_H
Vikas Manocha33913c52014-11-18 10:42:22 -080010#define CONFIG_SYS_DCACHE_OFF
Vikas Manocha33913c52014-11-18 10:42:22 -080011#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
Vikas Manocha32b9e712014-11-18 10:42:23 -080012
Vikas Manocha33913c52014-11-18 10:42:22 -080013#define CONFIG_SYS_CORTEX_R4
14
Vikas Manocha33913c52014-11-18 10:42:22 -080015/* ram memory-related information */
16#define CONFIG_NR_DRAM_BANKS 1
17#define PHYS_SDRAM_1 0x00000000
18#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
19#define PHYS_SDRAM_1_SIZE 0x00198000
20
21#define CONFIG_ENV_SIZE 0x10000
Vikas Manochaf6533532015-07-02 18:29:37 -070022#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
23#define CONFIG_ENV_OFFSET 0x30000
Vikas Manocha33913c52014-11-18 10:42:22 -080024#define CONFIG_ENV_ADDR \
25 (PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE)
Vikas Manocha33913c52014-11-18 10:42:22 -080026#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024)
27
28/* serial port (PL011) configuration */
Vikas Manocha0860b6a2014-12-01 12:27:54 -080029#define CONFIG_PL01X_SERIAL
Vikas Manocha33913c52014-11-18 10:42:22 -080030
31/* user interface */
Vikas Manocha7f34a692014-11-18 10:42:24 -080032#define CONFIG_SYS_CBSIZE 1024
Vikas Manocha33913c52014-11-18 10:42:22 -080033
34/* MISC */
35#define CONFIG_SYS_LOAD_ADDR 0x00000000
Vikas Manochad70864c2014-12-01 12:27:53 -080036#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
Vikas Manocha33913c52014-11-18 10:42:22 -080037#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000
38#define CONFIG_SYS_INIT_SP_OFFSET \
39 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Bin Meng75574052016-02-05 19:30:11 -080040/* U-Boot Load Address */
Vikas Manocha33913c52014-11-18 10:42:22 -080041#define CONFIG_SYS_TEXT_BASE 0x00010000
42#define CONFIG_SYS_INIT_SP_ADDR \
43 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
44
Vikas Manocha32b9e712014-11-18 10:42:23 -080045/* GMAC related configs */
46
47#define CONFIG_MII
Vikas Manocha32b9e712014-11-18 10:42:23 -080048#define CONFIG_DW_ALTDESCRIPTOR
Vikas Manocha32b9e712014-11-18 10:42:23 -080049
50/* Command support defines */
Vikas Manocha32b9e712014-11-18 10:42:23 -080051#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
52
Vikas Manocha7f34a692014-11-18 10:42:24 -080053#define CONFIG_SYS_MEMTEST_START 0x0000
54#define CONFIG_SYS_MEMTEST_END 1024*1024
Vikas Manocha7f34a692014-11-18 10:42:24 -080055
56/* Misc configuration */
57#define CONFIG_SYS_LONGHELP
58#define CONFIG_CMDLINE_EDITING
59
Vikas Manocha7f34a692014-11-18 10:42:24 -080060#define CONFIG_BOOTCOMMAND "go 0x40040000"
Stefan Roese83da3f12015-05-18 14:08:23 +020061
Vikas Manocha8cc062f2015-07-02 18:29:41 -070062/*
63+ * QSPI support
64+ */
65#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
Vikas Manocha8cc062f2015-07-02 18:29:41 -070066#define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000
Vikas Manocha8cc062f2015-07-02 18:29:41 -070067
Vikas Manocha8cc062f2015-07-02 18:29:41 -070068#endif
69
Vikas Manocha33913c52014-11-18 10:42:22 -080070#endif /* __CONFIG_H */