Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 2 | /* |
| 3 | dm9000.c: Version 1.2 12/15/2003 |
| 4 | |
| 5 | A Davicom DM9000 ISA NIC fast Ethernet driver for Linux. |
| 6 | Copyright (C) 1997 Sten Wang |
| 7 | |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 8 | (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. |
| 9 | |
| 10 | V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 11 | 06/22/2001 Support DM9801 progrmming |
| 12 | E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000 |
| 13 | E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200 |
| 14 | R17 = (R17 & 0xfff0) | NF + 3 |
| 15 | E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200 |
| 16 | R17 = (R17 & 0xfff0) | NF |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 17 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 18 | v1.00 modify by simon 2001.9.5 |
Wolfgang Denk | ec7fbf5 | 2013-10-04 17:43:24 +0200 | [diff] [blame] | 19 | change for kernel 2.4.x |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 20 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 21 | v1.1 11/09/2001 fix force mode bug |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 22 | |
| 23 | v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>: |
| 24 | Fixed phy reset. |
| 25 | Added tx/rx 32 bit mode. |
| 26 | Cleaned up for kernel merge. |
| 27 | |
| 28 | -------------------------------------- |
| 29 | |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 30 | 12/15/2003 Initial port to u-boot by |
Wolfgang Denk | 62fb2b4 | 2021-09-27 17:42:39 +0200 | [diff] [blame] | 31 | Sascha Hauer <saschahauer@web.de> |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 32 | |
| 33 | 06/03/2008 Remy Bohmer <linux@bohmer.net> |
Remy Bohmer | eec38a1 | 2008-06-03 15:26:25 +0200 | [diff] [blame] | 34 | - Fixed the driver to work with DM9000A. |
| 35 | (check on ISR receive status bit before reading the |
| 36 | FIFO as described in DM9000 programming guide and |
| 37 | application notes) |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 38 | - Added autodetect of databus width. |
Remy Bohmer | f4329dc | 2008-06-03 15:26:22 +0200 | [diff] [blame] | 39 | - Made debug code compile again. |
Remy Bohmer | 16cb264 | 2008-06-03 15:26:23 +0200 | [diff] [blame] | 40 | - Adapt eth_send such that it matches the DM9000* |
| 41 | application notes. Needed to make it work properly |
| 42 | for DM9000A. |
Remy Bohmer | 2f13d2c | 2008-06-03 15:26:24 +0200 | [diff] [blame] | 43 | - Adapted reset procedure to match DM9000 application |
| 44 | notes (i.e. double reset) |
Remy Bohmer | 61b8dbd | 2008-06-03 15:26:26 +0200 | [diff] [blame] | 45 | - some minor code cleanups |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 46 | These changes are tested with DM9000{A,EP,E} together |
Remy Bohmer | cd9a36c | 2009-05-03 12:11:40 +0200 | [diff] [blame] | 47 | with a 200MHz Atmel AT91SAM9261 core |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 48 | |
Andrew Dyer | a62f5d4 | 2008-08-26 17:03:38 -0500 | [diff] [blame] | 49 | TODO: external MII is not functional, only internal at the moment. |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 50 | */ |
| 51 | |
| 52 | #include <common.h> |
| 53 | #include <command.h> |
| 54 | #include <net.h> |
| 55 | #include <asm/io.h> |
Remy Bohmer | cd9a36c | 2009-05-03 12:11:40 +0200 | [diff] [blame] | 56 | #include <dm9000.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 57 | #include <linux/delay.h> |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 58 | |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 59 | #include "dm9000x.h" |
| 60 | |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 61 | /* Structure/enum declaration ------------------------------- */ |
| 62 | typedef struct board_info { |
| 63 | u32 runt_length_counter; /* counter: RX length < 64byte */ |
| 64 | u32 long_length_counter; /* counter: RX length > 1514byte */ |
| 65 | u32 reset_counter; /* counter: RESET */ |
| 66 | u32 reset_tx_timeout; /* RESET caused by TX Timeout */ |
| 67 | u32 reset_rx_status; /* RESET caused by RX Statsus wrong */ |
| 68 | u16 tx_pkt_cnt; |
| 69 | u16 queue_start_addr; |
| 70 | u16 dbug_cnt; |
| 71 | u8 phy_addr; |
| 72 | u8 device_wait_reset; /* device state */ |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 73 | unsigned char srom[128]; |
Remy Bohmer | 90d1fed | 2008-06-05 13:03:36 +0200 | [diff] [blame] | 74 | void (*outblk)(volatile void *data_ptr, int count); |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 75 | void (*inblk)(void *data_ptr, int count); |
Marek Vasut | 5248e56 | 2022-04-13 04:15:25 +0200 | [diff] [blame] | 76 | void (*rx_status)(u16 *rxstatus, u16 *rxlen); |
Remy Bohmer | 7eefd92 | 2009-05-02 21:49:18 +0200 | [diff] [blame] | 77 | struct eth_device netdev; |
Remy Bohmer | 61b8dbd | 2008-06-03 15:26:26 +0200 | [diff] [blame] | 78 | } board_info_t; |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 79 | static board_info_t dm9000_info; |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 80 | |
Remy Bohmer | 7eefd92 | 2009-05-02 21:49:18 +0200 | [diff] [blame] | 81 | |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 82 | /* function declaration ------------------------------------- */ |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 83 | static int dm9000_probe(void); |
Andy Fleming | 0d2df96 | 2011-03-22 22:49:13 -0500 | [diff] [blame] | 84 | static u16 dm9000_phy_read(int); |
| 85 | static void dm9000_phy_write(int, u16); |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 86 | static u8 dm9000_ior(int); |
| 87 | static void dm9000_iow(int reg, u8 value); |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 88 | |
| 89 | /* DM9000 network board routine ---------------------------- */ |
Jason Jin | c74c436 | 2011-08-25 15:46:43 +0800 | [diff] [blame] | 90 | #ifndef CONFIG_DM9000_BYTE_SWAPPED |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 91 | #define dm9000_outb(d,r) writeb(d, (volatile u8 *)(r)) |
| 92 | #define dm9000_outw(d,r) writew(d, (volatile u16 *)(r)) |
| 93 | #define dm9000_outl(d,r) writel(d, (volatile u32 *)(r)) |
| 94 | #define dm9000_inb(r) readb((volatile u8 *)(r)) |
| 95 | #define dm9000_inw(r) readw((volatile u16 *)(r)) |
| 96 | #define dm9000_inl(r) readl((volatile u32 *)(r)) |
Jason Jin | c74c436 | 2011-08-25 15:46:43 +0800 | [diff] [blame] | 97 | #else |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 98 | #define dm9000_outb(d, r) __raw_writeb(d, r) |
| 99 | #define dm9000_outw(d, r) __raw_writew(d, r) |
| 100 | #define dm9000_outl(d, r) __raw_writel(d, r) |
| 101 | #define dm9000_inb(r) __raw_readb(r) |
| 102 | #define dm9000_inw(r) __raw_readw(r) |
| 103 | #define dm9000_inl(r) __raw_readl(r) |
Jason Jin | c74c436 | 2011-08-25 15:46:43 +0800 | [diff] [blame] | 104 | #endif |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 105 | |
Marek Vasut | 52006d2 | 2022-04-13 04:15:27 +0200 | [diff] [blame^] | 106 | #ifdef DEBUG |
| 107 | static void dm9000_dump_packet(const char *func, u8 *packet, int length) |
| 108 | { |
| 109 | int i; |
| 110 | |
| 111 | printf("%s: length: %d\n", func, length); |
| 112 | |
| 113 | for (i = 0; i < length; i++) { |
| 114 | if (i % 8 == 0) |
| 115 | printf("\n%s: %02x: ", func, i); |
| 116 | printf("%02x ", packet[i]); |
| 117 | } |
| 118 | |
| 119 | printf("\n"); |
| 120 | } |
| 121 | #else |
| 122 | static void dm9000_dump_packet(const char *func, u8 *packet, int length) {} |
| 123 | #endif |
| 124 | |
Remy Bohmer | 90d1fed | 2008-06-05 13:03:36 +0200 | [diff] [blame] | 125 | static void dm9000_outblk_8bit(volatile void *data_ptr, int count) |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 126 | { |
| 127 | int i; |
| 128 | for (i = 0; i < count; i++) |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 129 | dm9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA); |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 130 | } |
| 131 | |
Remy Bohmer | 90d1fed | 2008-06-05 13:03:36 +0200 | [diff] [blame] | 132 | static void dm9000_outblk_16bit(volatile void *data_ptr, int count) |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 133 | { |
| 134 | int i; |
| 135 | u32 tmplen = (count + 1) / 2; |
| 136 | |
| 137 | for (i = 0; i < tmplen; i++) |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 138 | dm9000_outw(((u16 *) data_ptr)[i], DM9000_DATA); |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 139 | } |
Remy Bohmer | 90d1fed | 2008-06-05 13:03:36 +0200 | [diff] [blame] | 140 | static void dm9000_outblk_32bit(volatile void *data_ptr, int count) |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 141 | { |
| 142 | int i; |
| 143 | u32 tmplen = (count + 3) / 4; |
| 144 | |
| 145 | for (i = 0; i < tmplen; i++) |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 146 | dm9000_outl(((u32 *) data_ptr)[i], DM9000_DATA); |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 147 | } |
| 148 | |
| 149 | static void dm9000_inblk_8bit(void *data_ptr, int count) |
| 150 | { |
| 151 | int i; |
| 152 | for (i = 0; i < count; i++) |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 153 | ((u8 *) data_ptr)[i] = dm9000_inb(DM9000_DATA); |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 154 | } |
| 155 | |
| 156 | static void dm9000_inblk_16bit(void *data_ptr, int count) |
| 157 | { |
| 158 | int i; |
| 159 | u32 tmplen = (count + 1) / 2; |
| 160 | |
| 161 | for (i = 0; i < tmplen; i++) |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 162 | ((u16 *) data_ptr)[i] = dm9000_inw(DM9000_DATA); |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 163 | } |
| 164 | static void dm9000_inblk_32bit(void *data_ptr, int count) |
| 165 | { |
| 166 | int i; |
| 167 | u32 tmplen = (count + 3) / 4; |
| 168 | |
| 169 | for (i = 0; i < tmplen; i++) |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 170 | ((u32 *) data_ptr)[i] = dm9000_inl(DM9000_DATA); |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 171 | } |
| 172 | |
Marek Vasut | 5248e56 | 2022-04-13 04:15:25 +0200 | [diff] [blame] | 173 | static void dm9000_rx_status_32bit(u16 *rxstatus, u16 *rxlen) |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 174 | { |
Remy Bohmer | 2e1604f | 2008-06-04 10:47:25 +0200 | [diff] [blame] | 175 | u32 tmpdata; |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 176 | |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 177 | dm9000_outb(DM9000_MRCMD, DM9000_IO); |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 178 | |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 179 | tmpdata = dm9000_inl(DM9000_DATA); |
Marek Vasut | 5248e56 | 2022-04-13 04:15:25 +0200 | [diff] [blame] | 180 | *rxstatus = __le16_to_cpu(tmpdata); |
| 181 | *rxlen = __le16_to_cpu(tmpdata >> 16); |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 182 | } |
| 183 | |
Marek Vasut | 5248e56 | 2022-04-13 04:15:25 +0200 | [diff] [blame] | 184 | static void dm9000_rx_status_16bit(u16 *rxstatus, u16 *rxlen) |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 185 | { |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 186 | dm9000_outb(DM9000_MRCMD, DM9000_IO); |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 187 | |
Marek Vasut | 5248e56 | 2022-04-13 04:15:25 +0200 | [diff] [blame] | 188 | *rxstatus = __le16_to_cpu(dm9000_inw(DM9000_DATA)); |
| 189 | *rxlen = __le16_to_cpu(dm9000_inw(DM9000_DATA)); |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 190 | } |
| 191 | |
Marek Vasut | 5248e56 | 2022-04-13 04:15:25 +0200 | [diff] [blame] | 192 | static void dm9000_rx_status_8bit(u16 *rxstatus, u16 *rxlen) |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 193 | { |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 194 | dm9000_outb(DM9000_MRCMD, DM9000_IO); |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 195 | |
Marek Vasut | 5248e56 | 2022-04-13 04:15:25 +0200 | [diff] [blame] | 196 | *rxstatus = |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 197 | __le16_to_cpu(dm9000_inb(DM9000_DATA) + |
| 198 | (dm9000_inb(DM9000_DATA) << 8)); |
Marek Vasut | 5248e56 | 2022-04-13 04:15:25 +0200 | [diff] [blame] | 199 | *rxlen = |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 200 | __le16_to_cpu(dm9000_inb(DM9000_DATA) + |
| 201 | (dm9000_inb(DM9000_DATA) << 8)); |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 202 | } |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 203 | |
| 204 | /* |
| 205 | Search DM9000 board, allocate space and register it |
| 206 | */ |
| 207 | int |
| 208 | dm9000_probe(void) |
| 209 | { |
| 210 | u32 id_val; |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 211 | id_val = dm9000_ior(DM9000_VIDL); |
| 212 | id_val |= dm9000_ior(DM9000_VIDH) << 8; |
| 213 | id_val |= dm9000_ior(DM9000_PIDL) << 16; |
| 214 | id_val |= dm9000_ior(DM9000_PIDH) << 24; |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 215 | if (id_val == DM9000_ID) { |
| 216 | printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE, |
| 217 | id_val); |
| 218 | return 0; |
| 219 | } else { |
| 220 | printf("dm9000 not found at 0x%08x id: 0x%08x\n", |
| 221 | CONFIG_DM9000_BASE, id_val); |
| 222 | return -1; |
| 223 | } |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 224 | } |
| 225 | |
| 226 | /* General Purpose dm9000 reset routine */ |
| 227 | static void |
| 228 | dm9000_reset(void) |
| 229 | { |
Marek Vasut | ed76122 | 2022-04-13 04:15:24 +0200 | [diff] [blame] | 230 | debug("resetting DM9000\n"); |
Remy Bohmer | 2f13d2c | 2008-06-03 15:26:24 +0200 | [diff] [blame] | 231 | |
| 232 | /* Reset DM9000, |
| 233 | see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */ |
| 234 | |
Andrew Dyer | a62f5d4 | 2008-08-26 17:03:38 -0500 | [diff] [blame] | 235 | /* DEBUG: Make all GPIO0 outputs, all others inputs */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 236 | dm9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT); |
Remy Bohmer | 2f13d2c | 2008-06-03 15:26:24 +0200 | [diff] [blame] | 237 | /* Step 1: Power internal PHY by writing 0 to GPIO0 pin */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 238 | dm9000_iow(DM9000_GPR, 0); |
Remy Bohmer | 2f13d2c | 2008-06-03 15:26:24 +0200 | [diff] [blame] | 239 | /* Step 2: Software reset */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 240 | dm9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); |
Remy Bohmer | 2f13d2c | 2008-06-03 15:26:24 +0200 | [diff] [blame] | 241 | |
| 242 | do { |
Marek Vasut | ed76122 | 2022-04-13 04:15:24 +0200 | [diff] [blame] | 243 | debug("resetting the DM9000, 1st reset\n"); |
Remy Bohmer | 2f13d2c | 2008-06-03 15:26:24 +0200 | [diff] [blame] | 244 | udelay(25); /* Wait at least 20 us */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 245 | } while (dm9000_ior(DM9000_NCR) & 1); |
Remy Bohmer | 2f13d2c | 2008-06-03 15:26:24 +0200 | [diff] [blame] | 246 | |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 247 | dm9000_iow(DM9000_NCR, 0); |
| 248 | dm9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */ |
Remy Bohmer | 2f13d2c | 2008-06-03 15:26:24 +0200 | [diff] [blame] | 249 | |
| 250 | do { |
Marek Vasut | ed76122 | 2022-04-13 04:15:24 +0200 | [diff] [blame] | 251 | debug("resetting the DM9000, 2nd reset\n"); |
Remy Bohmer | 2f13d2c | 2008-06-03 15:26:24 +0200 | [diff] [blame] | 252 | udelay(25); /* Wait at least 20 us */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 253 | } while (dm9000_ior(DM9000_NCR) & 1); |
Remy Bohmer | 2f13d2c | 2008-06-03 15:26:24 +0200 | [diff] [blame] | 254 | |
| 255 | /* Check whether the ethernet controller is present */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 256 | if ((dm9000_ior(DM9000_PIDL) != 0x0) || |
| 257 | (dm9000_ior(DM9000_PIDH) != 0x90)) |
Remy Bohmer | 2f13d2c | 2008-06-03 15:26:24 +0200 | [diff] [blame] | 258 | printf("ERROR: resetting DM9000 -> not responding\n"); |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 259 | } |
| 260 | |
Remy Bohmer | 7eefd92 | 2009-05-02 21:49:18 +0200 | [diff] [blame] | 261 | /* Initialize dm9000 board |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 262 | */ |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 263 | static int dm9000_init(struct eth_device *dev, struct bd_info *bd) |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 264 | { |
| 265 | int i, oft, lnk; |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 266 | u8 io_mode; |
| 267 | struct board_info *db = &dm9000_info; |
| 268 | |
Marek Vasut | ed76122 | 2022-04-13 04:15:24 +0200 | [diff] [blame] | 269 | debug("%s\n", __func__); |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 270 | |
| 271 | /* RESET device */ |
| 272 | dm9000_reset(); |
Andrew Dyer | a62f5d4 | 2008-08-26 17:03:38 -0500 | [diff] [blame] | 273 | |
| 274 | if (dm9000_probe() < 0) |
| 275 | return -1; |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 276 | |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 277 | /* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 278 | io_mode = dm9000_ior(DM9000_ISR) >> 6; |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 279 | |
| 280 | switch (io_mode) { |
| 281 | case 0x0: /* 16-bit mode */ |
| 282 | printf("DM9000: running in 16 bit mode\n"); |
| 283 | db->outblk = dm9000_outblk_16bit; |
| 284 | db->inblk = dm9000_inblk_16bit; |
| 285 | db->rx_status = dm9000_rx_status_16bit; |
| 286 | break; |
| 287 | case 0x01: /* 32-bit mode */ |
| 288 | printf("DM9000: running in 32 bit mode\n"); |
| 289 | db->outblk = dm9000_outblk_32bit; |
| 290 | db->inblk = dm9000_inblk_32bit; |
| 291 | db->rx_status = dm9000_rx_status_32bit; |
| 292 | break; |
| 293 | case 0x02: /* 8 bit mode */ |
| 294 | printf("DM9000: running in 8 bit mode\n"); |
| 295 | db->outblk = dm9000_outblk_8bit; |
| 296 | db->inblk = dm9000_inblk_8bit; |
| 297 | db->rx_status = dm9000_rx_status_8bit; |
| 298 | break; |
| 299 | default: |
| 300 | /* Assume 8 bit mode, will probably not work anyway */ |
| 301 | printf("DM9000: Undefined IO-mode:0x%x\n", io_mode); |
| 302 | db->outblk = dm9000_outblk_8bit; |
| 303 | db->inblk = dm9000_inblk_8bit; |
| 304 | db->rx_status = dm9000_rx_status_8bit; |
| 305 | break; |
| 306 | } |
| 307 | |
Andrew Dyer | a62f5d4 | 2008-08-26 17:03:38 -0500 | [diff] [blame] | 308 | /* Program operating register, only internal phy supported */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 309 | dm9000_iow(DM9000_NCR, 0x0); |
Remy Bohmer | 61b8dbd | 2008-06-03 15:26:26 +0200 | [diff] [blame] | 310 | /* TX Polling clear */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 311 | dm9000_iow(DM9000_TCR, 0); |
Remy Bohmer | 61b8dbd | 2008-06-03 15:26:26 +0200 | [diff] [blame] | 312 | /* Less 3Kb, 200us */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 313 | dm9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US); |
Remy Bohmer | 61b8dbd | 2008-06-03 15:26:26 +0200 | [diff] [blame] | 314 | /* Flow Control : High/Low Water */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 315 | dm9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); |
Remy Bohmer | 61b8dbd | 2008-06-03 15:26:26 +0200 | [diff] [blame] | 316 | /* SH FIXME: This looks strange! Flow Control */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 317 | dm9000_iow(DM9000_FCR, 0x0); |
Remy Bohmer | 61b8dbd | 2008-06-03 15:26:26 +0200 | [diff] [blame] | 318 | /* Special Mode */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 319 | dm9000_iow(DM9000_SMCR, 0); |
Remy Bohmer | 61b8dbd | 2008-06-03 15:26:26 +0200 | [diff] [blame] | 320 | /* clear TX status */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 321 | dm9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); |
Remy Bohmer | 61b8dbd | 2008-06-03 15:26:26 +0200 | [diff] [blame] | 322 | /* Clear interrupt status */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 323 | dm9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS); |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 324 | |
Ben Warren | 8707f62 | 2009-10-21 21:53:39 -0700 | [diff] [blame] | 325 | printf("MAC: %pM\n", dev->enetaddr); |
Joe Hershberger | 8ecdbed | 2015-04-08 01:41:04 -0500 | [diff] [blame] | 326 | if (!is_valid_ethaddr(dev->enetaddr)) { |
Andrew Ruder | 1c377d1 | 2013-10-22 19:09:02 -0500 | [diff] [blame] | 327 | printf("WARNING: Bad MAC address (uninitialized EEPROM?)\n"); |
Andrew Ruder | 1c377d1 | 2013-10-22 19:09:02 -0500 | [diff] [blame] | 328 | } |
Andrew Dyer | a62f5d4 | 2008-08-26 17:03:38 -0500 | [diff] [blame] | 329 | |
| 330 | /* fill device MAC address registers */ |
| 331 | for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 332 | dm9000_iow(oft, dev->enetaddr[i]); |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 333 | for (i = 0, oft = 0x16; i < 8; i++, oft++) |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 334 | dm9000_iow(oft, 0xff); |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 335 | |
| 336 | /* read back mac, just to be sure */ |
| 337 | for (i = 0, oft = 0x10; i < 6; i++, oft++) |
Marek Vasut | ed76122 | 2022-04-13 04:15:24 +0200 | [diff] [blame] | 338 | debug("%02x:", dm9000_ior(oft)); |
| 339 | debug("\n"); |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 340 | |
| 341 | /* Activate DM9000 */ |
Remy Bohmer | 61b8dbd | 2008-06-03 15:26:26 +0200 | [diff] [blame] | 342 | /* RX enable */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 343 | dm9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); |
Remy Bohmer | 61b8dbd | 2008-06-03 15:26:26 +0200 | [diff] [blame] | 344 | /* Enable TX/RX interrupt mask */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 345 | dm9000_iow(DM9000_IMR, IMR_PAR); |
Remy Bohmer | 61b8dbd | 2008-06-03 15:26:26 +0200 | [diff] [blame] | 346 | |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 347 | i = 0; |
Andy Fleming | 0d2df96 | 2011-03-22 22:49:13 -0500 | [diff] [blame] | 348 | while (!(dm9000_phy_read(1) & 0x20)) { /* autonegation complete bit */ |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 349 | udelay(1000); |
| 350 | i++; |
| 351 | if (i == 10000) { |
| 352 | printf("could not establish link\n"); |
| 353 | return 0; |
| 354 | } |
| 355 | } |
| 356 | |
| 357 | /* see what we've got */ |
Andy Fleming | 0d2df96 | 2011-03-22 22:49:13 -0500 | [diff] [blame] | 358 | lnk = dm9000_phy_read(17) >> 12; |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 359 | printf("operating at "); |
| 360 | switch (lnk) { |
| 361 | case 1: |
| 362 | printf("10M half duplex "); |
| 363 | break; |
| 364 | case 2: |
| 365 | printf("10M full duplex "); |
| 366 | break; |
| 367 | case 4: |
| 368 | printf("100M half duplex "); |
| 369 | break; |
| 370 | case 8: |
| 371 | printf("100M full duplex "); |
| 372 | break; |
| 373 | default: |
| 374 | printf("unknown: %d ", lnk); |
| 375 | break; |
| 376 | } |
| 377 | printf("mode\n"); |
| 378 | return 0; |
| 379 | } |
| 380 | |
| 381 | /* |
| 382 | Hardware start transmission. |
| 383 | Send a packet to media from the upper layer. |
| 384 | */ |
Joe Hershberger | ab1ac41 | 2012-05-21 14:45:23 +0000 | [diff] [blame] | 385 | static int dm9000_send(struct eth_device *netdev, void *packet, int length) |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 386 | { |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 387 | int tmo; |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 388 | struct board_info *db = &dm9000_info; |
| 389 | |
Marek Vasut | 52006d2 | 2022-04-13 04:15:27 +0200 | [diff] [blame^] | 390 | dm9000_dump_packet(__func__ , packet, length); |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 391 | |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 392 | dm9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */ |
Remy Bohmer | 16cb264 | 2008-06-03 15:26:23 +0200 | [diff] [blame] | 393 | |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 394 | /* Move data to DM9000 TX RAM */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 395 | dm9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */ |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 396 | |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 397 | /* push the data to the TX-fifo */ |
Remy Bohmer | 90d1fed | 2008-06-05 13:03:36 +0200 | [diff] [blame] | 398 | (db->outblk)(packet, length); |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 399 | |
| 400 | /* Set TX length to DM9000 */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 401 | dm9000_iow(DM9000_TXPLL, length & 0xff); |
| 402 | dm9000_iow(DM9000_TXPLH, (length >> 8) & 0xff); |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 403 | |
| 404 | /* Issue TX polling command */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 405 | dm9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 406 | |
| 407 | /* wait for end of transmission */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 408 | tmo = get_timer(0) + 5 * CONFIG_SYS_HZ; |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 409 | while ( !(dm9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) || |
| 410 | !(dm9000_ior(DM9000_ISR) & IMR_PTM) ) { |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 411 | if (get_timer(0) >= tmo) { |
| 412 | printf("transmission timeout\n"); |
| 413 | break; |
| 414 | } |
| 415 | } |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 416 | dm9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */ |
Remy Bohmer | 16cb264 | 2008-06-03 15:26:23 +0200 | [diff] [blame] | 417 | |
Marek Vasut | ed76122 | 2022-04-13 04:15:24 +0200 | [diff] [blame] | 418 | debug("transmit done\n\n"); |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 419 | return 0; |
| 420 | } |
| 421 | |
| 422 | /* |
| 423 | Stop the interface. |
| 424 | The interface is stopped when it is brought. |
| 425 | */ |
Remy Bohmer | 7eefd92 | 2009-05-02 21:49:18 +0200 | [diff] [blame] | 426 | static void dm9000_halt(struct eth_device *netdev) |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 427 | { |
Marek Vasut | ed76122 | 2022-04-13 04:15:24 +0200 | [diff] [blame] | 428 | debug("%s\n", __func__); |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 429 | |
| 430 | /* RESET devie */ |
Andy Fleming | 0d2df96 | 2011-03-22 22:49:13 -0500 | [diff] [blame] | 431 | dm9000_phy_write(0, 0x8000); /* PHY RESET */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 432 | dm9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */ |
| 433 | dm9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */ |
| 434 | dm9000_iow(DM9000_RCR, 0x00); /* Disable RX */ |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 435 | } |
| 436 | |
| 437 | /* |
| 438 | Received a packet and pass to upper layer |
| 439 | */ |
Remy Bohmer | 7eefd92 | 2009-05-02 21:49:18 +0200 | [diff] [blame] | 440 | static int dm9000_rx(struct eth_device *netdev) |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 441 | { |
Joe Hershberger | 9f09a36 | 2015-04-08 01:41:06 -0500 | [diff] [blame] | 442 | u8 rxbyte; |
| 443 | u8 *rdptr = (u8 *)net_rx_packets[0]; |
Marek Vasut | 5248e56 | 2022-04-13 04:15:25 +0200 | [diff] [blame] | 444 | u16 rxstatus, rxlen = 0; |
Remy Bohmer | 5f63bf4 | 2008-06-03 15:26:21 +0200 | [diff] [blame] | 445 | struct board_info *db = &dm9000_info; |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 446 | |
Remy Bohmer | eec38a1 | 2008-06-03 15:26:25 +0200 | [diff] [blame] | 447 | /* Check packet ready or not, we must check |
| 448 | the ISR status first for DM9000A */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 449 | if (!(dm9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */ |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 450 | return 0; |
| 451 | |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 452 | dm9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */ |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 453 | |
Remy Bohmer | eec38a1 | 2008-06-03 15:26:25 +0200 | [diff] [blame] | 454 | /* There is _at least_ 1 package in the fifo, read them all */ |
| 455 | for (;;) { |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 456 | dm9000_ior(DM9000_MRCMDX); /* Dummy read */ |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 457 | |
Remy Bohmer | 90d1fed | 2008-06-05 13:03:36 +0200 | [diff] [blame] | 458 | /* Get most updated data, |
| 459 | only look at bits 0:1, See application notes DM9000 */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 460 | rxbyte = dm9000_inb(DM9000_DATA) & 0x03; |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 461 | |
Remy Bohmer | eec38a1 | 2008-06-03 15:26:25 +0200 | [diff] [blame] | 462 | /* Status check: this byte must be 0 or 1 */ |
| 463 | if (rxbyte > DM9000_PKT_RDY) { |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 464 | dm9000_iow(DM9000_RCR, 0x00); /* Stop Device */ |
| 465 | dm9000_iow(DM9000_ISR, 0x80); /* Stop INT request */ |
Remy Bohmer | eec38a1 | 2008-06-03 15:26:25 +0200 | [diff] [blame] | 466 | printf("DM9000 error: status check fail: 0x%x\n", |
| 467 | rxbyte); |
| 468 | return 0; |
| 469 | } |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 470 | |
Remy Bohmer | eec38a1 | 2008-06-03 15:26:25 +0200 | [diff] [blame] | 471 | if (rxbyte != DM9000_PKT_RDY) |
| 472 | return 0; /* No packet received, ignore */ |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 473 | |
Marek Vasut | ed76122 | 2022-04-13 04:15:24 +0200 | [diff] [blame] | 474 | debug("receiving packet\n"); |
Remy Bohmer | eec38a1 | 2008-06-03 15:26:25 +0200 | [diff] [blame] | 475 | |
| 476 | /* A packet ready now & Get status/length */ |
Marek Vasut | 5248e56 | 2022-04-13 04:15:25 +0200 | [diff] [blame] | 477 | (db->rx_status)(&rxstatus, &rxlen); |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 478 | |
Marek Vasut | 5248e56 | 2022-04-13 04:15:25 +0200 | [diff] [blame] | 479 | debug("rx status: 0x%04x rx len: %d\n", rxstatus, rxlen); |
Remy Bohmer | eec38a1 | 2008-06-03 15:26:25 +0200 | [diff] [blame] | 480 | |
| 481 | /* Move data from DM9000 */ |
| 482 | /* Read received packet from RX SRAM */ |
Marek Vasut | 5248e56 | 2022-04-13 04:15:25 +0200 | [diff] [blame] | 483 | (db->inblk)(rdptr, rxlen); |
Remy Bohmer | eec38a1 | 2008-06-03 15:26:25 +0200 | [diff] [blame] | 484 | |
Marek Vasut | 5248e56 | 2022-04-13 04:15:25 +0200 | [diff] [blame] | 485 | if ((rxstatus & 0xbf00) || (rxlen < 0x40) |
| 486 | || (rxlen > DM9000_PKT_MAX)) { |
| 487 | if (rxstatus & 0x100) { |
Remy Bohmer | eec38a1 | 2008-06-03 15:26:25 +0200 | [diff] [blame] | 488 | printf("rx fifo error\n"); |
| 489 | } |
Marek Vasut | 5248e56 | 2022-04-13 04:15:25 +0200 | [diff] [blame] | 490 | if (rxstatus & 0x200) { |
Remy Bohmer | eec38a1 | 2008-06-03 15:26:25 +0200 | [diff] [blame] | 491 | printf("rx crc error\n"); |
| 492 | } |
Marek Vasut | 5248e56 | 2022-04-13 04:15:25 +0200 | [diff] [blame] | 493 | if (rxstatus & 0x8000) { |
Remy Bohmer | eec38a1 | 2008-06-03 15:26:25 +0200 | [diff] [blame] | 494 | printf("rx length error\n"); |
| 495 | } |
Marek Vasut | 5248e56 | 2022-04-13 04:15:25 +0200 | [diff] [blame] | 496 | if (rxlen > DM9000_PKT_MAX) { |
Remy Bohmer | eec38a1 | 2008-06-03 15:26:25 +0200 | [diff] [blame] | 497 | printf("rx length too big\n"); |
| 498 | dm9000_reset(); |
| 499 | } |
| 500 | } else { |
Marek Vasut | 52006d2 | 2022-04-13 04:15:27 +0200 | [diff] [blame^] | 501 | dm9000_dump_packet(__func__ , rdptr, rxlen); |
Remy Bohmer | eec38a1 | 2008-06-03 15:26:25 +0200 | [diff] [blame] | 502 | |
Marek Vasut | ed76122 | 2022-04-13 04:15:24 +0200 | [diff] [blame] | 503 | debug("passing packet to upper layer\n"); |
Marek Vasut | 5248e56 | 2022-04-13 04:15:25 +0200 | [diff] [blame] | 504 | net_process_received_packet(net_rx_packets[0], rxlen); |
Remy Bohmer | eec38a1 | 2008-06-03 15:26:25 +0200 | [diff] [blame] | 505 | } |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 506 | } |
| 507 | return 0; |
| 508 | } |
| 509 | |
| 510 | /* |
| 511 | Read a word data from SROM |
| 512 | */ |
Remy Bohmer | cd9a36c | 2009-05-03 12:11:40 +0200 | [diff] [blame] | 513 | #if !defined(CONFIG_DM9000_NO_SROM) |
| 514 | void dm9000_read_srom_word(int offset, u8 *to) |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 515 | { |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 516 | dm9000_iow(DM9000_EPAR, offset); |
| 517 | dm9000_iow(DM9000_EPCR, 0x4); |
stefano babic | edb0687 | 2007-08-21 15:50:33 +0200 | [diff] [blame] | 518 | udelay(8000); |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 519 | dm9000_iow(DM9000_EPCR, 0x0); |
| 520 | to[0] = dm9000_ior(DM9000_EPDRL); |
| 521 | to[1] = dm9000_ior(DM9000_EPDRH); |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 522 | } |
| 523 | |
Remy Bohmer | cd9a36c | 2009-05-03 12:11:40 +0200 | [diff] [blame] | 524 | void dm9000_write_srom_word(int offset, u16 val) |
stefano babic | 6708a60 | 2007-08-30 23:01:49 +0200 | [diff] [blame] | 525 | { |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 526 | dm9000_iow(DM9000_EPAR, offset); |
| 527 | dm9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff)); |
| 528 | dm9000_iow(DM9000_EPDRL, (val & 0xff)); |
| 529 | dm9000_iow(DM9000_EPCR, 0x12); |
stefano babic | 6708a60 | 2007-08-30 23:01:49 +0200 | [diff] [blame] | 530 | udelay(8000); |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 531 | dm9000_iow(DM9000_EPCR, 0); |
stefano babic | 6708a60 | 2007-08-30 23:01:49 +0200 | [diff] [blame] | 532 | } |
Remy Bohmer | cd9a36c | 2009-05-03 12:11:40 +0200 | [diff] [blame] | 533 | #endif |
Ben Warren | 8707f62 | 2009-10-21 21:53:39 -0700 | [diff] [blame] | 534 | |
| 535 | static void dm9000_get_enetaddr(struct eth_device *dev) |
| 536 | { |
| 537 | #if !defined(CONFIG_DM9000_NO_SROM) |
| 538 | int i; |
| 539 | for (i = 0; i < 3; i++) |
| 540 | dm9000_read_srom_word(i, dev->enetaddr + (2 * i)); |
| 541 | #endif |
| 542 | } |
stefano babic | 6708a60 | 2007-08-30 23:01:49 +0200 | [diff] [blame] | 543 | |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 544 | /* |
| 545 | Read a byte from I/O port |
| 546 | */ |
| 547 | static u8 |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 548 | dm9000_ior(int reg) |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 549 | { |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 550 | dm9000_outb(reg, DM9000_IO); |
| 551 | return dm9000_inb(DM9000_DATA); |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 552 | } |
| 553 | |
| 554 | /* |
| 555 | Write a byte to I/O port |
| 556 | */ |
| 557 | static void |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 558 | dm9000_iow(int reg, u8 value) |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 559 | { |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 560 | dm9000_outb(reg, DM9000_IO); |
| 561 | dm9000_outb(value, DM9000_DATA); |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 562 | } |
| 563 | |
| 564 | /* |
| 565 | Read a word from phyxcer |
| 566 | */ |
| 567 | static u16 |
Andy Fleming | 0d2df96 | 2011-03-22 22:49:13 -0500 | [diff] [blame] | 568 | dm9000_phy_read(int reg) |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 569 | { |
| 570 | u16 val; |
| 571 | |
| 572 | /* Fill the phyxcer register into REG_0C */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 573 | dm9000_iow(DM9000_EPAR, DM9000_PHY | reg); |
| 574 | dm9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */ |
Remy Bohmer | 61b8dbd | 2008-06-03 15:26:26 +0200 | [diff] [blame] | 575 | udelay(100); /* Wait read complete */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 576 | dm9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */ |
| 577 | val = (dm9000_ior(DM9000_EPDRH) << 8) | dm9000_ior(DM9000_EPDRL); |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 578 | |
| 579 | /* The read data keeps on REG_0D & REG_0E */ |
Marek Vasut | ed76122 | 2022-04-13 04:15:24 +0200 | [diff] [blame] | 580 | debug("dm9000_phy_read(0x%x): 0x%x\n", reg, val); |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 581 | return val; |
| 582 | } |
| 583 | |
| 584 | /* |
| 585 | Write a word to phyxcer |
| 586 | */ |
| 587 | static void |
Andy Fleming | 0d2df96 | 2011-03-22 22:49:13 -0500 | [diff] [blame] | 588 | dm9000_phy_write(int reg, u16 value) |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 589 | { |
| 590 | |
| 591 | /* Fill the phyxcer register into REG_0C */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 592 | dm9000_iow(DM9000_EPAR, DM9000_PHY | reg); |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 593 | |
| 594 | /* Fill the written data into REG_0D & REG_0E */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 595 | dm9000_iow(DM9000_EPDRL, (value & 0xff)); |
| 596 | dm9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff)); |
| 597 | dm9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */ |
Remy Bohmer | 61b8dbd | 2008-06-03 15:26:26 +0200 | [diff] [blame] | 598 | udelay(500); /* Wait write complete */ |
Marek Vasut | eb2749a | 2022-04-13 04:15:23 +0200 | [diff] [blame] | 599 | dm9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */ |
Marek Vasut | ed76122 | 2022-04-13 04:15:24 +0200 | [diff] [blame] | 600 | debug("dm9000_phy_write(reg:0x%x, value:0x%x)\n", reg, value); |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 601 | } |
Remy Bohmer | 7eefd92 | 2009-05-02 21:49:18 +0200 | [diff] [blame] | 602 | |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 603 | int dm9000_initialize(struct bd_info *bis) |
Remy Bohmer | 7eefd92 | 2009-05-02 21:49:18 +0200 | [diff] [blame] | 604 | { |
| 605 | struct eth_device *dev = &(dm9000_info.netdev); |
| 606 | |
Ben Warren | 8707f62 | 2009-10-21 21:53:39 -0700 | [diff] [blame] | 607 | /* Load MAC address from EEPROM */ |
| 608 | dm9000_get_enetaddr(dev); |
| 609 | |
Remy Bohmer | 7eefd92 | 2009-05-02 21:49:18 +0200 | [diff] [blame] | 610 | dev->init = dm9000_init; |
| 611 | dev->halt = dm9000_halt; |
| 612 | dev->send = dm9000_send; |
| 613 | dev->recv = dm9000_rx; |
Ben Whitten | 34fd6c9 | 2015-12-30 13:05:58 +0000 | [diff] [blame] | 614 | strcpy(dev->name, "dm9000"); |
Remy Bohmer | 7eefd92 | 2009-05-02 21:49:18 +0200 | [diff] [blame] | 615 | |
| 616 | eth_register(dev); |
| 617 | |
| 618 | return 0; |
| 619 | } |