Svyatoslav Ryhel | 88fd156 | 2023-06-30 10:29:04 +0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | |
| 3 | #include <dt-bindings/input/input.h> |
Svyatoslav Ryhel | 88fd156 | 2023-06-30 10:29:04 +0300 | [diff] [blame] | 4 | #include "tegra30.dtsi" |
| 5 | |
| 6 | / { |
| 7 | chosen { |
| 8 | stdout-path = &uarta; |
| 9 | }; |
| 10 | |
| 11 | aliases { |
| 12 | i2c0 = &pwr_i2c; |
| 13 | |
| 14 | mmc0 = &sdmmc4; /* eMMC */ |
| 15 | |
| 16 | rtc0 = &pmic; |
| 17 | rtc1 = "/rtc@7000e000"; |
| 18 | |
| 19 | usb0 = &usb1; |
| 20 | }; |
| 21 | |
| 22 | memory { |
| 23 | device_type = "memory"; |
| 24 | reg = <0x80000000 0x40000000>; |
| 25 | }; |
| 26 | |
| 27 | host1x@50000000 { |
| 28 | dc@54200000 { |
| 29 | nvidia,180-rotation; |
| 30 | rgb { |
| 31 | status = "okay"; |
| 32 | |
| 33 | nvidia,panel = <&panel>; |
| 34 | }; |
| 35 | }; |
| 36 | }; |
| 37 | |
| 38 | gpio@6000d000 { |
| 39 | volume-buttons-hog { |
| 40 | gpio-hog; |
| 41 | gpios = <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>, |
| 42 | <TEGRA_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; |
| 43 | output-low; |
| 44 | }; |
| 45 | }; |
| 46 | |
Svyatoslav Ryhel | 51f70c1 | 2023-11-27 18:16:50 +0200 | [diff] [blame^] | 47 | pinmux@70000868 { |
| 48 | pinctrl-names = "default"; |
| 49 | pinctrl-0 = <&state_default>; |
| 50 | |
| 51 | state_default: pinmux { |
| 52 | clk_32k_out_pa0 { |
| 53 | nvidia,pins = "clk_32k_out_pa0"; |
| 54 | nvidia,function = "blink"; |
| 55 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 56 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 57 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 58 | }; |
| 59 | uart3_cts_n_pa1 { |
| 60 | nvidia,pins = "uart3_cts_n_pa1", |
| 61 | "uart3_rxd_pw7"; |
| 62 | nvidia,function = "uartc"; |
| 63 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 64 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 65 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 66 | }; |
| 67 | dap2_fs_pa2 { |
| 68 | nvidia,pins = "dap2_fs_pa2", |
| 69 | "dap2_sclk_pa3", |
| 70 | "dap2_din_pa4", |
| 71 | "dap2_dout_pa5"; |
| 72 | nvidia,function = "i2s1"; |
| 73 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 74 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 75 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 76 | }; |
| 77 | sdmmc3_clk_pa6 { |
| 78 | nvidia,pins = "sdmmc3_clk_pa6"; |
| 79 | nvidia,function = "sdmmc3"; |
| 80 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 81 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 82 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 83 | }; |
| 84 | sdmmc3_cmd_pa7 { |
| 85 | nvidia,pins = "sdmmc3_cmd_pa7", |
| 86 | "sdmmc3_dat3_pb4", |
| 87 | "sdmmc3_dat2_pb5", |
| 88 | "sdmmc3_dat1_pb6", |
| 89 | "sdmmc3_dat0_pb7", |
| 90 | "sdmmc3_dat4_pd1", |
| 91 | "sdmmc3_dat6_pd3", |
| 92 | "sdmmc3_dat7_pd4"; |
| 93 | nvidia,function = "sdmmc3"; |
| 94 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 95 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 96 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 97 | }; |
| 98 | gmi_a17_pb0 { |
| 99 | nvidia,pins = "gmi_a17_pb0", |
| 100 | "gmi_a18_pb1"; |
| 101 | nvidia,function = "uartd"; |
| 102 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 103 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 104 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 105 | }; |
| 106 | lcd_pwr0_pb2 { |
| 107 | nvidia,pins = "lcd_pwr0_pb2", |
| 108 | "lcd_pwr1_pc1", |
| 109 | "lcd_m1_pw1"; |
| 110 | nvidia,function = "displaya"; |
| 111 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 112 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 113 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 114 | }; |
| 115 | lcd_pclk_pb3 { |
| 116 | nvidia,pins = "lcd_pclk_pb3", |
| 117 | "lcd_d0_pe0", |
| 118 | "lcd_d1_pe1", |
| 119 | "lcd_d2_pe2", |
| 120 | "lcd_d3_pe3", |
| 121 | "lcd_d4_pe4", |
| 122 | "lcd_d5_pe5", |
| 123 | "lcd_d6_pe6", |
| 124 | "lcd_d7_pe7", |
| 125 | "lcd_d8_pf0", |
| 126 | "lcd_d9_pf1", |
| 127 | "lcd_d10_pf2", |
| 128 | "lcd_d11_pf3", |
| 129 | "lcd_d12_pf4", |
| 130 | "lcd_d13_pf5", |
| 131 | "lcd_d14_pf6", |
| 132 | "lcd_d15_pf7", |
| 133 | "lcd_de_pj1", |
| 134 | "lcd_hsync_pj3", |
| 135 | "lcd_vsync_pj4", |
| 136 | "lcd_d16_pm0", |
| 137 | "lcd_d17_pm1", |
| 138 | "lcd_d18_pm2", |
| 139 | "lcd_d19_pm3", |
| 140 | "lcd_d20_pm4", |
| 141 | "lcd_d21_pm5", |
| 142 | "lcd_d22_pm6", |
| 143 | "lcd_d23_pm7", |
| 144 | "lcd_cs0_n_pn4", |
| 145 | "lcd_sdout_pn5", |
| 146 | "lcd_dc0_pn6", |
| 147 | "lcd_cs1_n_pw0", |
| 148 | "lcd_sdin_pz2", |
| 149 | "lcd_sck_pz4"; |
| 150 | nvidia,function = "displaya"; |
| 151 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 152 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 153 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 154 | }; |
| 155 | uart3_rts_n_pc0 { |
| 156 | nvidia,pins = "uart3_rts_n_pc0", |
| 157 | "uart3_txd_pw6"; |
| 158 | nvidia,function = "uartc"; |
| 159 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 160 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 161 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 162 | }; |
| 163 | uart2_txd_pc2 { |
| 164 | nvidia,pins = "uart2_txd_pc2", |
| 165 | "uart2_rts_n_pj6"; |
| 166 | nvidia,function = "uartb"; |
| 167 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 168 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 169 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 170 | }; |
| 171 | uart2_rxd_pc3 { |
| 172 | nvidia,pins = "uart2_rxd_pc3", |
| 173 | "uart2_cts_n_pj5"; |
| 174 | nvidia,function = "uartb"; |
| 175 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 176 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 177 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 178 | }; |
| 179 | gen1_i2c_scl_pc4 { |
| 180 | nvidia,pins = "gen1_i2c_scl_pc4", |
| 181 | "gen1_i2c_sda_pc5"; |
| 182 | nvidia,function = "i2c1"; |
| 183 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 184 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 185 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 186 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 187 | }; |
| 188 | gmi_wp_n_pc7 { |
| 189 | nvidia,pins = "gmi_wp_n_pc7", |
| 190 | "gmi_wait_pi7", |
| 191 | "gmi_cs4_n_pk2", |
| 192 | "gmi_cs3_n_pk4"; |
| 193 | nvidia,function = "rsvd1"; |
| 194 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 195 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 196 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 197 | }; |
| 198 | gmi_ad12_ph4 { |
| 199 | nvidia,pins = "gmi_ad12_ph4", |
| 200 | "gmi_cs0_n_pj0", |
| 201 | "gmi_cs1_n_pj2", |
| 202 | "gmi_cs2_n_pk3"; |
| 203 | nvidia,function = "rsvd1"; |
| 204 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 205 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 206 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 207 | }; |
| 208 | sdmmc3_dat5_pd0 { |
| 209 | nvidia,pins = "sdmmc3_dat5_pd0"; |
| 210 | nvidia,function = "sdmmc3"; |
| 211 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 212 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 213 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 214 | }; |
| 215 | gmi_ad0_pg0 { |
| 216 | nvidia,pins = "gmi_ad0_pg0", |
| 217 | "gmi_ad1_pg1", |
| 218 | "gmi_ad14_ph6", |
| 219 | "pu1"; |
| 220 | nvidia,function = "rsvd1"; |
| 221 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 222 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 223 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 224 | }; |
| 225 | gmi_ad2_pg2 { |
| 226 | nvidia,pins = "gmi_ad2_pg2", |
| 227 | "gmi_ad3_pg3", |
| 228 | "gmi_ad6_pg6", |
| 229 | "gmi_ad7_pg7"; |
| 230 | nvidia,function = "rsvd1"; |
| 231 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 232 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 233 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 234 | }; |
| 235 | gmi_ad4_pg4 { |
| 236 | nvidia,pins = "gmi_ad4_pg4", |
| 237 | "gmi_ad5_pg5"; |
| 238 | nvidia,function = "nand"; |
| 239 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 240 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 241 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 242 | }; |
| 243 | gmi_ad8_ph0 { |
| 244 | nvidia,pins = "gmi_ad8_ph0"; |
| 245 | nvidia,function = "pwm0"; |
| 246 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 247 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 248 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 249 | }; |
| 250 | gmi_ad9_ph1 { |
| 251 | nvidia,pins = "gmi_ad9_ph1"; |
| 252 | nvidia,function = "rsvd4"; |
| 253 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 254 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 255 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 256 | }; |
| 257 | gmi_ad10_ph2 { |
| 258 | nvidia,pins = "gmi_ad10_ph2"; |
| 259 | nvidia,function = "pwm2"; |
| 260 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 261 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 262 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 263 | }; |
| 264 | gmi_ad11_ph3 { |
| 265 | nvidia,pins = "gmi_ad11_ph3"; |
| 266 | nvidia,function = "pwm3"; |
| 267 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 268 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 269 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 270 | }; |
| 271 | gmi_ad13_ph5 { |
| 272 | nvidia,pins = "gmi_ad13_ph5", |
| 273 | "gmi_wr_n_pi0", |
| 274 | "gmi_oe_n_pi1", |
| 275 | "gmi_adv_n_pk0"; |
| 276 | nvidia,function = "rsvd1"; |
| 277 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 278 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 279 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 280 | }; |
| 281 | gmi_ad15_ph7 { |
| 282 | nvidia,pins = "gmi_ad15_ph7"; |
| 283 | nvidia,function = "rsvd1"; |
| 284 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 285 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 286 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 287 | }; |
| 288 | gmi_dqs_pi2 { |
| 289 | nvidia,pins = "gmi_dqs_pi2", |
| 290 | "pu2", |
| 291 | "pv1"; |
| 292 | nvidia,function = "rsvd1"; |
| 293 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 294 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 295 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 296 | }; |
| 297 | gmi_rst_n_pi4 { |
| 298 | nvidia,pins = "gmi_rst_n_pi4"; |
| 299 | nvidia,function = "nand"; |
| 300 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 301 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 302 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 303 | }; |
| 304 | gmi_iordy_pi5 { |
| 305 | nvidia,pins = "gmi_iordy_pi5"; |
| 306 | nvidia,function = "rsvd1"; |
| 307 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 308 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 309 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 310 | }; |
| 311 | gmi_cs7_n_pi6 { |
| 312 | nvidia,pins = "gmi_cs7_n_pi6", |
| 313 | "gmi_clk_pk1"; |
| 314 | nvidia,function = "nand"; |
| 315 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 316 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 317 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 318 | }; |
| 319 | gmi_a16_pj7 { |
| 320 | nvidia,pins = "gmi_a16_pj7", |
| 321 | "gmi_a19_pk7"; |
| 322 | nvidia,function = "uartd"; |
| 323 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 324 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 325 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 326 | }; |
| 327 | spdif_out_pk5 { |
| 328 | nvidia,pins = "spdif_out_pk5"; |
| 329 | nvidia,function = "spdif"; |
| 330 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 331 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 332 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 333 | }; |
| 334 | spdif_in_pk6 { |
| 335 | nvidia,pins = "spdif_in_pk6"; |
| 336 | nvidia,function = "spdif"; |
| 337 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 338 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 339 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 340 | }; |
| 341 | dap1_fs_pn0 { |
| 342 | nvidia,pins = "dap1_fs_pn0", |
| 343 | "dap1_din_pn1", |
| 344 | "dap1_dout_pn2", |
| 345 | "dap1_sclk_pn3"; |
| 346 | nvidia,function = "i2s0"; |
| 347 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 348 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 349 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 350 | }; |
| 351 | hdmi_int_pn7 { |
| 352 | nvidia,pins = "hdmi_int_pn7"; |
| 353 | nvidia,function = "hdmi"; |
| 354 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 355 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 356 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 357 | }; |
| 358 | ulpi_data7_po0 { |
| 359 | nvidia,pins = "ulpi_data7_po0"; |
| 360 | nvidia,function = "uarta"; |
| 361 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 362 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 363 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 364 | }; |
| 365 | ulpi_data3_po4 { |
| 366 | nvidia,pins = "ulpi_data3_po4"; |
| 367 | nvidia,function = "ulpi"; |
| 368 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 369 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 370 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 371 | }; |
| 372 | dap3_fs_pp0 { |
| 373 | nvidia,pins = "dap3_fs_pp0"; |
| 374 | nvidia,function = "i2s2"; |
| 375 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 376 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 377 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 378 | }; |
| 379 | dap4_fs_pp4 { |
| 380 | nvidia,pins = "dap4_fs_pp4", |
| 381 | "dap4_din_pp5", |
| 382 | "dap4_dout_pp6", |
| 383 | "dap4_sclk_pp7"; |
| 384 | nvidia,function = "i2s3"; |
| 385 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 386 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 387 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 388 | }; |
| 389 | kb_col0_pq0 { |
| 390 | nvidia,pins = "kb_col0_pq0", |
| 391 | "kb_col1_pq1", |
| 392 | "kb_row1_pr1"; |
| 393 | nvidia,function = "kbc"; |
| 394 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 395 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 396 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 397 | }; |
| 398 | kb_col2_pq2 { |
| 399 | nvidia,pins = "kb_col2_pq2", |
| 400 | "kb_col3_pq3"; |
| 401 | nvidia,function = "rsvd4"; |
| 402 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 403 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 404 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 405 | }; |
| 406 | kb_col4_pq4 { |
| 407 | nvidia,pins = "kb_col4_pq4", |
| 408 | "kb_col5_pq5", |
| 409 | "kb_col7_pq7", |
| 410 | "kb_row2_pr2", |
| 411 | "kb_row4_pr4", |
| 412 | "kb_row5_pr5", |
| 413 | "kb_row14_ps6"; |
| 414 | nvidia,function = "kbc"; |
| 415 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 416 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 417 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 418 | }; |
| 419 | kb_row0_pr0 { |
| 420 | nvidia,pins = "kb_row0_pr0"; |
| 421 | nvidia,function = "rsvd4"; |
| 422 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 423 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 424 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 425 | }; |
| 426 | kb_row6_pr6 { |
| 427 | nvidia,pins = "kb_row6_pr6", |
| 428 | "kb_row8_ps0", |
| 429 | "kb_row9_ps1", |
| 430 | "kb_row10_ps2"; |
| 431 | nvidia,function = "kbc"; |
| 432 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 433 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 434 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 435 | }; |
| 436 | kb_row11_ps3 { |
| 437 | nvidia,pins = "kb_row11_ps3", |
| 438 | "kb_row12_ps4"; |
| 439 | nvidia,function = "kbc"; |
| 440 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 441 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 442 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 443 | }; |
| 444 | gen2_i2c_scl_pt5 { |
| 445 | nvidia,pins = "gen2_i2c_scl_pt5", |
| 446 | "gen2_i2c_sda_pt6"; |
| 447 | nvidia,function = "i2c2"; |
| 448 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 449 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 450 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 451 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 452 | }; |
| 453 | sdmmc4_cmd_pt7 { |
| 454 | nvidia,pins = "sdmmc4_cmd_pt7", |
| 455 | "sdmmc4_dat0_paa0", |
| 456 | "sdmmc4_dat1_paa1", |
| 457 | "sdmmc4_dat2_paa2", |
| 458 | "sdmmc4_dat3_paa3", |
| 459 | "sdmmc4_dat4_paa4", |
| 460 | "sdmmc4_dat5_paa5", |
| 461 | "sdmmc4_dat6_paa6", |
| 462 | "sdmmc4_dat7_paa7"; |
| 463 | nvidia,function = "sdmmc4"; |
| 464 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 465 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 466 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 467 | }; |
| 468 | pu0 { |
| 469 | nvidia,pins = "pu0", |
| 470 | "pu6"; |
| 471 | nvidia,function = "rsvd4"; |
| 472 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 473 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 474 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 475 | }; |
| 476 | jtag_rtck_pu7 { |
| 477 | nvidia,pins = "jtag_rtck_pu7"; |
| 478 | nvidia,function = "rtck"; |
| 479 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 480 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 481 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 482 | }; |
| 483 | pv0 { |
| 484 | nvidia,pins = "pv0"; |
| 485 | nvidia,function = "rsvd1"; |
| 486 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 487 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 488 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 489 | }; |
| 490 | ddc_scl_pv4 { |
| 491 | nvidia,pins = "ddc_scl_pv4", |
| 492 | "ddc_sda_pv5"; |
| 493 | nvidia,function = "i2c4"; |
| 494 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 495 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 496 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 497 | }; |
| 498 | crt_hsync_pv6 { |
| 499 | nvidia,pins = "crt_hsync_pv6", |
| 500 | "crt_vsync_pv7"; |
| 501 | nvidia,function = "crt"; |
| 502 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 503 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 504 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 505 | }; |
| 506 | spi2_cs1_n_pw2 { |
| 507 | nvidia,pins = "spi2_cs1_n_pw2", |
| 508 | "spi2_miso_px1", |
| 509 | "spi2_sck_px2"; |
| 510 | nvidia,function = "spi2"; |
| 511 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 512 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 513 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 514 | }; |
| 515 | clk1_out_pw4 { |
| 516 | nvidia,pins = "clk1_out_pw4"; |
| 517 | nvidia,function = "extperiph1"; |
| 518 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 519 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 520 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 521 | }; |
| 522 | clk2_out_pw5 { |
| 523 | nvidia,pins = "clk2_out_pw5"; |
| 524 | nvidia,function = "extperiph2"; |
| 525 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 526 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 527 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 528 | }; |
| 529 | spi2_cs0_n_px3 { |
| 530 | nvidia,pins = "spi2_cs0_n_px3"; |
| 531 | nvidia,function = "spi6"; |
| 532 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 533 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 534 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 535 | }; |
| 536 | spi1_mosi_px4 { |
| 537 | nvidia,pins = "spi1_mosi_px4", |
| 538 | "spi1_cs0_n_px6"; |
| 539 | nvidia,function = "spi1"; |
| 540 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 541 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 542 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 543 | }; |
| 544 | ulpi_clk_py0 { |
| 545 | nvidia,pins = "ulpi_clk_py0", |
| 546 | "ulpi_dir_py1"; |
| 547 | nvidia,function = "ulpi"; |
| 548 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 549 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 550 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 551 | }; |
| 552 | sdmmc1_dat3_py4 { |
| 553 | nvidia,pins = "sdmmc1_dat3_py4", |
| 554 | "sdmmc1_dat2_py5", |
| 555 | "sdmmc1_dat1_py6", |
| 556 | "sdmmc1_dat0_py7", |
| 557 | "sdmmc1_cmd_pz1"; |
| 558 | nvidia,function = "sdmmc1"; |
| 559 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 560 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 561 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 562 | }; |
| 563 | sdmmc1_clk_pz0 { |
| 564 | nvidia,pins = "sdmmc1_clk_pz0"; |
| 565 | nvidia,function = "sdmmc1"; |
| 566 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 567 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 568 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 569 | }; |
| 570 | lcd_wr_n_pz3 { |
| 571 | nvidia,pins = "lcd_wr_n_pz3"; |
| 572 | nvidia,function = "displaya"; |
| 573 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 574 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 575 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 576 | }; |
| 577 | sys_clk_req_pz5 { |
| 578 | nvidia,pins = "sys_clk_req_pz5"; |
| 579 | nvidia,function = "sysclk"; |
| 580 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 581 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 582 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 583 | }; |
| 584 | pwr_i2c_scl_pz6 { |
| 585 | nvidia,pins = "pwr_i2c_scl_pz6", |
| 586 | "pwr_i2c_sda_pz7"; |
| 587 | nvidia,function = "i2cpwr"; |
| 588 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 589 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 590 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 591 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 592 | }; |
| 593 | pbb0 { |
| 594 | nvidia,pins = "pbb0", |
| 595 | "pcc1"; |
| 596 | nvidia,function = "rsvd2"; |
| 597 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 598 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 599 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 600 | }; |
| 601 | cam_i2c_scl_pbb1 { |
| 602 | nvidia,pins = "cam_i2c_scl_pbb1", |
| 603 | "cam_i2c_sda_pbb2"; |
| 604 | nvidia,function = "i2c3"; |
| 605 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 606 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 607 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 608 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| 609 | }; |
| 610 | pbb3 { |
| 611 | nvidia,pins = "pbb3"; |
| 612 | nvidia,function = "vgp3"; |
| 613 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 614 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 615 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 616 | }; |
| 617 | pbb4 { |
| 618 | nvidia,pins = "pbb4"; |
| 619 | nvidia,function = "vgp4"; |
| 620 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 621 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 622 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 623 | }; |
| 624 | pbb5 { |
| 625 | nvidia,pins = "pbb5"; |
| 626 | nvidia,function = "vgp5"; |
| 627 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 628 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 629 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 630 | }; |
| 631 | pbb6 { |
| 632 | nvidia,pins = "pbb6"; |
| 633 | nvidia,function = "vgp6"; |
| 634 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 635 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 636 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 637 | }; |
| 638 | pbb7 { |
| 639 | nvidia,pins = "pbb7", |
| 640 | "pcc2"; |
| 641 | nvidia,function = "i2s4"; |
| 642 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 643 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 644 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 645 | }; |
| 646 | cam_mclk_pcc0 { |
| 647 | nvidia,pins = "cam_mclk_pcc0"; |
| 648 | nvidia,function = "vi_alt3"; |
| 649 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 650 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 651 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 652 | }; |
| 653 | sdmmc4_rst_n_pcc3 { |
| 654 | nvidia,pins = "sdmmc4_rst_n_pcc3"; |
| 655 | nvidia,function = "rsvd2"; |
| 656 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 657 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 658 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 659 | }; |
| 660 | sdmmc4_clk_pcc4 { |
| 661 | nvidia,pins = "sdmmc4_clk_pcc4"; |
| 662 | nvidia,function = "sdmmc4"; |
| 663 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 664 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 665 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 666 | }; |
| 667 | clk2_req_pcc5 { |
| 668 | nvidia,pins = "clk2_req_pcc5"; |
| 669 | nvidia,function = "dap"; |
| 670 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 671 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 672 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 673 | }; |
| 674 | pex_l2_rst_n_pcc6 { |
| 675 | nvidia,pins = "pex_l2_rst_n_pcc6", |
| 676 | "pex_l2_clkreq_n_pcc7"; |
| 677 | nvidia,function = "pcie"; |
| 678 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 679 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 680 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 681 | }; |
| 682 | pex_wake_n_pdd3 { |
| 683 | nvidia,pins = "pex_wake_n_pdd3", |
| 684 | "pex_l2_prsnt_n_pdd7"; |
| 685 | nvidia,function = "pcie"; |
| 686 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 687 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 688 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 689 | }; |
| 690 | clk3_out_pee0 { |
| 691 | nvidia,pins = "clk3_out_pee0"; |
| 692 | nvidia,function = "extperiph3"; |
| 693 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 694 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 695 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 696 | }; |
| 697 | clk1_req_pee2 { |
| 698 | nvidia,pins = "clk1_req_pee2"; |
| 699 | nvidia,function = "dap"; |
| 700 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 701 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 702 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| 703 | }; |
| 704 | hdmi_cec_pee3 { |
| 705 | nvidia,pins = "hdmi_cec_pee3"; |
| 706 | nvidia,function = "cec"; |
| 707 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 708 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 709 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 710 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| 711 | }; |
| 712 | owr { |
| 713 | nvidia,pins = "owr"; |
| 714 | nvidia,function = "owr"; |
| 715 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 716 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 717 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| 718 | }; |
| 719 | drive_dap1 { |
| 720 | nvidia,pins = "drive_dap1", |
| 721 | "drive_dap2", |
| 722 | "drive_dbg", |
| 723 | "drive_at5", |
| 724 | "drive_gme", |
| 725 | "drive_ddc", |
| 726 | "drive_ao1", |
| 727 | "drive_uart3"; |
| 728 | nvidia,high-speed-mode = <0>; |
| 729 | nvidia,schmitt = <TEGRA_PIN_ENABLE>; |
| 730 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; |
| 731 | nvidia,pull-down-strength = <31>; |
| 732 | nvidia,pull-up-strength = <31>; |
| 733 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 734 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| 735 | }; |
| 736 | drive_sdio1 { |
| 737 | nvidia,pins = "drive_sdio1", |
| 738 | "drive_sdio3"; |
| 739 | nvidia,high-speed-mode = <0>; |
| 740 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
| 741 | nvidia,pull-down-strength = <46>; |
| 742 | nvidia,pull-up-strength = <42>; |
| 743 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; |
| 744 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; |
| 745 | }; |
| 746 | drive_gma { |
| 747 | nvidia,pins = "drive_gma", |
| 748 | "drive_gmb", |
| 749 | "drive_gmc", |
| 750 | "drive_gmd"; |
| 751 | nvidia,pull-down-strength = <9>; |
| 752 | nvidia,pull-up-strength = <9>; |
| 753 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; |
| 754 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; |
| 755 | }; |
| 756 | }; |
| 757 | }; |
| 758 | |
Svyatoslav Ryhel | 88fd156 | 2023-06-30 10:29:04 +0300 | [diff] [blame] | 759 | uarta: serial@70006000 { |
| 760 | status = "okay"; |
| 761 | }; |
| 762 | |
| 763 | pwm: pwm@7000a000 { |
| 764 | status = "okay"; |
| 765 | }; |
| 766 | |
| 767 | pwr_i2c: i2c@7000d000 { |
| 768 | status = "okay"; |
| 769 | clock-frequency = <400000>; |
| 770 | }; |
| 771 | |
| 772 | sdmmc4: sdhci@78000600 { |
| 773 | status = "okay"; |
| 774 | bus-width = <8>; |
| 775 | non-removable; |
Svyatoslav Ryhel | caa4a46 | 2023-10-03 09:36:41 +0300 | [diff] [blame] | 776 | |
| 777 | vmmc-supply = <&vcore_emmc>; |
| 778 | vqmmc-supply = <&vdd_1v8_vio>; |
Svyatoslav Ryhel | 88fd156 | 2023-06-30 10:29:04 +0300 | [diff] [blame] | 779 | }; |
| 780 | |
| 781 | usb1: usb@7d000000 { |
| 782 | status = "okay"; |
| 783 | dr_mode = "otg"; |
| 784 | }; |
| 785 | |
Svyatoslav Ryhel | 6c43861 | 2023-08-25 20:23:14 +0300 | [diff] [blame] | 786 | usb-phy@7d000000 { |
| 787 | status = "okay"; |
| 788 | nvidia,hssync-start-delay = <0>; |
| 789 | nvidia,xcvr-lsfslew = <2>; |
| 790 | nvidia,xcvr-lsrslew = <2>; |
| 791 | }; |
| 792 | |
Svyatoslav Ryhel | 88fd156 | 2023-06-30 10:29:04 +0300 | [diff] [blame] | 793 | backlight: backlight { |
| 794 | compatible = "pwm-backlight"; |
| 795 | |
| 796 | enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; |
| 797 | power-supply = <&vdd_5v0_bl>; |
| 798 | pwms = <&pwm 0 50000>; |
| 799 | |
| 800 | brightness-levels = <1 35 70 105 140 175 210 255>; |
| 801 | default-brightness-level = <5>; |
| 802 | }; |
| 803 | |
| 804 | /* PMIC has a built-in 32KHz oscillator which is used by PMC */ |
| 805 | clk32k_in: clock-32k { |
| 806 | compatible = "fixed-clock"; |
| 807 | #clock-cells = <0>; |
| 808 | clock-frequency = <32768>; |
| 809 | clock-output-names = "pmic-oscillator"; |
| 810 | }; |
| 811 | |
| 812 | gpio-keys { |
| 813 | compatible = "gpio-keys"; |
| 814 | |
| 815 | key-power { |
| 816 | label = "Power"; |
| 817 | gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; |
| 818 | linux,code = <KEY_ENTER>; |
| 819 | }; |
| 820 | |
| 821 | key-volume-up { |
| 822 | label = "Volume Up"; |
| 823 | gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; |
| 824 | linux,code = <KEY_UP>; |
| 825 | }; |
| 826 | |
| 827 | key-volume-down { |
| 828 | label = "Volume Down"; |
| 829 | gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; |
| 830 | linux,code = <KEY_DOWN>; |
| 831 | }; |
| 832 | }; |
| 833 | |
| 834 | panel: panel { |
| 835 | compatible = "simple-panel"; |
| 836 | |
| 837 | power-supply = <&vdd_pnl_reg>; |
| 838 | enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>; |
| 839 | |
| 840 | backlight = <&backlight>; |
| 841 | |
| 842 | display-timings { |
| 843 | timing@0 { |
| 844 | /* 1280x800@60Hz */ |
| 845 | clock-frequency = <68000000>; |
| 846 | |
| 847 | hactive = <800>; |
| 848 | hfront-porch = <24>; |
| 849 | hback-porch = <32>; |
| 850 | hsync-len = <24>; |
| 851 | |
| 852 | vactive = <1280>; |
| 853 | vfront-porch = <5>; |
| 854 | vback-porch = <32>; |
| 855 | vsync-len = <1>; |
| 856 | }; |
| 857 | }; |
| 858 | }; |
| 859 | |
| 860 | vdd_pnl_reg: regulator-pnl { |
| 861 | compatible = "regulator-fixed"; |
| 862 | regulator-name = "vdd_panel"; |
| 863 | regulator-min-microvolt = <3300000>; |
| 864 | regulator-max-microvolt = <3300000>; |
| 865 | gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; |
| 866 | enable-active-high; |
| 867 | }; |
| 868 | |
| 869 | vdd_5v0_bl: regulator-bl { |
| 870 | compatible = "regulator-fixed"; |
| 871 | regulator-name = "vdd_5v0_bl"; |
| 872 | regulator-min-microvolt = <5000000>; |
| 873 | regulator-max-microvolt = <5000000>; |
Svyatoslav Ryhel | 88fd156 | 2023-06-30 10:29:04 +0300 | [diff] [blame] | 874 | gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; |
| 875 | enable-active-high; |
| 876 | }; |
| 877 | }; |