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git01.mediatek.com / filogic / uboot / 51f70c1f520becbfd4a6192506207366348d931b / . / arch / arm / dts / rk356x-u-boot.dtsi
blob: 354b6958e5721f107f9e74997c1efe0318f3d797 [file] [log] [blame]
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * (C) Copyright 2021 Rockchip Electronics Co., Ltd
4 */
5
Quentin Schulzd9ffa5e2022-09-02 15:10:52 +0200[diff] [blame]6#include "rockchip-u-boot.dtsi"
7
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]8/ {
9 aliases {
10 mmc0 = &sdhci;
11 mmc1 = &sdmmc0;
Jonas Karlmanaec644c2023-07-28 12:05:40 +0000[diff] [blame]12 spi4 = &sfc;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]13 };
14
Nico Cheng16bc03c2021-10-26 10:42:20 +0800[diff] [blame]15 chosen {
Jonas Karlmandab889e2023-07-28 11:53:08 +0000[diff] [blame]16 u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
Nico Cheng16bc03c2021-10-26 10:42:20 +0800[diff] [blame]17 };
18
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]19 dmc: dmc {
20 compatible = "rockchip,rk3568-dmc";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]21 bootph-all;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]22 status = "okay";
23 };
Jonas Karlmanbe56bb52023-02-22 22:44:41 +0000[diff] [blame]24
25 otp: nvmem@fe38c000 {
26 compatible = "rockchip,rk3568-otp";
27 reg = <0x0 0xfe38c000 0x0 0x4000>;
28 #address-cells = <1>;
29 #size-cells = <1>;
30 status = "okay";
31
32 cpu_id: id@a {
33 reg = <0x0a 0x10>;
34 };
35 };
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]36};
37
Jonas Karlman13e3dc92023-05-17 18:26:29 +0000[diff] [blame]38&xin24m {
39 bootph-all;
40 status = "okay";
41};
42
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]43&cru {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]44 bootph-all;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]45 status = "okay";
46};
47
48&pmucru {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-all;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]50 status = "okay";
51};
52
53&grf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]54 bootph-all;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]55 status = "okay";
56};
57
58&pmugrf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]59 bootph-all;
Joseph Chen868dc1d2021-06-02 15:58:23 +0800[diff] [blame]60 status = "okay";
61};
Nico Cheng16bc03c2021-10-26 10:42:20 +0800[diff] [blame]62
Jonas Karlmanf216c612023-07-28 11:53:07 +0000[diff] [blame]63&pinctrl {
64 bootph-all;
65};
66
Jonas Karlmanc6391352023-08-03 21:11:54 +0000[diff] [blame]67&pcfg_pull_none_smt {
68 bootph-all;
69};
70
Jonas Karlmanf216c612023-07-28 11:53:07 +0000[diff] [blame]71&pcfg_pull_none {
72 bootph-all;
73};
74
75&pcfg_pull_up_drv_level_2 {
76 bootph-all;
77};
78
79&pcfg_pull_up {
80 bootph-all;
81};
82
83&emmc_bus8 {
84 bootph-all;
85};
86
87&emmc_clk {
88 bootph-all;
89};
90
91&emmc_cmd {
92 bootph-all;
93};
94
95&emmc_datastrobe {
96 bootph-all;
97};
98
99&emmc_rstnout {
100 bootph-all;
101};
102
103&fspi_pins {
104 bootph-all;
105};
106
Jonas Karlmanc6391352023-08-03 21:11:54 +0000[diff] [blame]107&i2c0_xfer {
108 bootph-all;
109};
110
Jonas Karlmanf216c612023-07-28 11:53:07 +0000[diff] [blame]111&sdmmc0_bus4 {
112 bootph-all;
113};
114
115&sdmmc0_clk {
116 bootph-all;
117};
118
119&sdmmc0_cmd {
120 bootph-all;
121};
122
123&sdmmc0_det {
124 bootph-all;
125};
126
127&sdmmc0_pwren {
128 bootph-all;
129};
130
131&uart2m0_xfer {
132 bootph-all;
133};
134
FUKAUMI Naoki98dc96a2022-10-04 01:30:30 +0000[diff] [blame]135&sdhci {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]136 bootph-pre-ram;
Jonas Karlmane8841382023-08-04 09:34:01 +0000[diff] [blame]137 max-frequency = <200000000>;
Nico Cheng16bc03c2021-10-26 10:42:20 +0800[diff] [blame]138};
139
FUKAUMI Naoki98dc96a2022-10-04 01:30:30 +0000[diff] [blame]140&sdmmc0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]141 bootph-pre-ram;
Nico Cheng16bc03c2021-10-26 10:42:20 +0800[diff] [blame]142};
Jonas Karlmana9d8d532023-05-17 18:26:35 +0000[diff] [blame]143
144#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
145&binman {
146 simple-bin-spi {
147 mkimage {
148 args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
149 offset = <0x8000>;
150 };
151 };
152};
153#endif