Stefano Babic | 99a42ed | 2011-10-07 23:27:34 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Porting to u-boot: |
| 3 | * |
| 4 | * (C) Copyright 2011 |
| 5 | * Stefano Babic, DENX Software Engineering, sbabic@denx.de. |
| 6 | * |
| 7 | * Copyright (C) 2008-2009 MontaVista Software Inc. |
| 8 | * Copyright (C) 2008-2009 Texas Instruments Inc |
| 9 | * |
| 10 | * Based on the LCD driver for TI Avalanche processors written by |
| 11 | * Ajay Singh and Shalom Hai. |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or modify |
| 14 | * it under the terms of the GNU General Public License as published by |
| 15 | * the Free Software Foundation; either version 2 of the License, or |
| 16 | * (at your option)any later version. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 21 | * GNU General Public License for more details. |
| 22 | * |
| 23 | * You should have received a copy of the GNU General Public License |
| 24 | * along with this program; if not, write to the Free Software |
| 25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 26 | */ |
| 27 | |
| 28 | #include <common.h> |
| 29 | #include <malloc.h> |
| 30 | #include <video_fb.h> |
| 31 | #include <linux/list.h> |
| 32 | #include <linux/fb.h> |
| 33 | |
| 34 | #include <asm/errno.h> |
| 35 | #include <asm/io.h> |
| 36 | #include <asm/arch/hardware.h> |
| 37 | |
| 38 | #include "videomodes.h" |
| 39 | #include <asm/arch/da8xx-fb.h> |
| 40 | |
| 41 | #define DRIVER_NAME "da8xx_lcdc" |
| 42 | |
| 43 | /* LCD Status Register */ |
| 44 | #define LCD_END_OF_FRAME1 (1 << 9) |
| 45 | #define LCD_END_OF_FRAME0 (1 << 8) |
| 46 | #define LCD_PL_LOAD_DONE (1 << 6) |
| 47 | #define LCD_FIFO_UNDERFLOW (1 << 5) |
| 48 | #define LCD_SYNC_LOST (1 << 2) |
| 49 | |
| 50 | /* LCD DMA Control Register */ |
| 51 | #define LCD_DMA_BURST_SIZE(x) ((x) << 4) |
| 52 | #define LCD_DMA_BURST_1 0x0 |
| 53 | #define LCD_DMA_BURST_2 0x1 |
| 54 | #define LCD_DMA_BURST_4 0x2 |
| 55 | #define LCD_DMA_BURST_8 0x3 |
| 56 | #define LCD_DMA_BURST_16 0x4 |
| 57 | #define LCD_END_OF_FRAME_INT_ENA (1 << 2) |
| 58 | #define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0) |
| 59 | |
| 60 | /* LCD Control Register */ |
| 61 | #define LCD_CLK_DIVISOR(x) ((x) << 8) |
| 62 | #define LCD_RASTER_MODE 0x01 |
| 63 | |
| 64 | /* LCD Raster Control Register */ |
| 65 | #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20) |
| 66 | #define PALETTE_AND_DATA 0x00 |
| 67 | #define PALETTE_ONLY 0x01 |
| 68 | #define DATA_ONLY 0x02 |
| 69 | |
| 70 | #define LCD_MONO_8BIT_MODE (1 << 9) |
| 71 | #define LCD_RASTER_ORDER (1 << 8) |
| 72 | #define LCD_TFT_MODE (1 << 7) |
| 73 | #define LCD_UNDERFLOW_INT_ENA (1 << 6) |
| 74 | #define LCD_PL_ENABLE (1 << 4) |
| 75 | #define LCD_MONOCHROME_MODE (1 << 1) |
| 76 | #define LCD_RASTER_ENABLE (1 << 0) |
| 77 | #define LCD_TFT_ALT_ENABLE (1 << 23) |
| 78 | #define LCD_STN_565_ENABLE (1 << 24) |
| 79 | |
| 80 | /* LCD Raster Timing 2 Register */ |
| 81 | #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16) |
| 82 | #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8) |
| 83 | #define LCD_SYNC_CTRL (1 << 25) |
| 84 | #define LCD_SYNC_EDGE (1 << 24) |
| 85 | #define LCD_INVERT_PIXEL_CLOCK (1 << 22) |
| 86 | #define LCD_INVERT_LINE_CLOCK (1 << 21) |
| 87 | #define LCD_INVERT_FRAME_CLOCK (1 << 20) |
| 88 | |
| 89 | /* LCD Block */ |
| 90 | struct da8xx_lcd_regs { |
| 91 | u32 revid; |
| 92 | u32 ctrl; |
| 93 | u32 stat; |
| 94 | u32 lidd_ctrl; |
| 95 | u32 lidd_cs0_conf; |
| 96 | u32 lidd_cs0_addr; |
| 97 | u32 lidd_cs0_data; |
| 98 | u32 lidd_cs1_conf; |
| 99 | u32 lidd_cs1_addr; |
| 100 | u32 lidd_cs1_data; |
| 101 | u32 raster_ctrl; |
| 102 | u32 raster_timing_0; |
| 103 | u32 raster_timing_1; |
| 104 | u32 raster_timing_2; |
| 105 | u32 raster_subpanel; |
| 106 | u32 reserved; |
| 107 | u32 dma_ctrl; |
| 108 | u32 dma_frm_buf_base_addr_0; |
| 109 | u32 dma_frm_buf_ceiling_addr_0; |
| 110 | u32 dma_frm_buf_base_addr_1; |
| 111 | u32 dma_frm_buf_ceiling_addr_1; |
| 112 | }; |
| 113 | |
| 114 | #define LCD_NUM_BUFFERS 1 |
| 115 | |
| 116 | #define WSI_TIMEOUT 50 |
| 117 | #define PALETTE_SIZE 256 |
| 118 | #define LEFT_MARGIN 64 |
| 119 | #define RIGHT_MARGIN 64 |
| 120 | #define UPPER_MARGIN 32 |
| 121 | #define LOWER_MARGIN 32 |
| 122 | |
| 123 | #define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP) |
Stefano Babic | 99a42ed | 2011-10-07 23:27:34 +0000 | [diff] [blame] | 124 | |
| 125 | static struct da8xx_lcd_regs *da8xx_fb_reg_base; |
| 126 | |
| 127 | DECLARE_GLOBAL_DATA_PTR; |
| 128 | |
| 129 | /* graphics setup */ |
| 130 | static GraphicDevice gpanel; |
| 131 | static const struct da8xx_panel *lcd_panel; |
| 132 | static struct fb_info *da8xx_fb_info; |
| 133 | static int bits_x_pixel; |
| 134 | |
| 135 | static inline unsigned int lcdc_read(u32 *addr) |
| 136 | { |
| 137 | return (unsigned int)readl(addr); |
| 138 | } |
| 139 | |
| 140 | static inline void lcdc_write(unsigned int val, u32 *addr) |
| 141 | { |
| 142 | writel(val, addr); |
| 143 | } |
| 144 | |
| 145 | struct da8xx_fb_par { |
| 146 | u32 p_palette_base; |
| 147 | unsigned char *v_palette_base; |
| 148 | dma_addr_t vram_phys; |
| 149 | unsigned long vram_size; |
| 150 | void *vram_virt; |
| 151 | unsigned int dma_start; |
| 152 | unsigned int dma_end; |
| 153 | struct clk *lcdc_clk; |
| 154 | int irq; |
| 155 | unsigned short pseudo_palette[16]; |
| 156 | unsigned int palette_sz; |
| 157 | unsigned int pxl_clk; |
| 158 | int blank; |
| 159 | int vsync_flag; |
| 160 | int vsync_timeout; |
| 161 | }; |
| 162 | |
| 163 | |
| 164 | /* Variable Screen Information */ |
| 165 | static struct fb_var_screeninfo da8xx_fb_var = { |
| 166 | .xoffset = 0, |
| 167 | .yoffset = 0, |
| 168 | .transp = {0, 0, 0}, |
| 169 | .nonstd = 0, |
| 170 | .activate = 0, |
| 171 | .height = -1, |
| 172 | .width = -1, |
| 173 | .pixclock = 46666, /* 46us - AUO display */ |
| 174 | .accel_flags = 0, |
| 175 | .left_margin = LEFT_MARGIN, |
| 176 | .right_margin = RIGHT_MARGIN, |
| 177 | .upper_margin = UPPER_MARGIN, |
| 178 | .lower_margin = LOWER_MARGIN, |
| 179 | .sync = 0, |
| 180 | .vmode = FB_VMODE_NONINTERLACED |
| 181 | }; |
| 182 | |
| 183 | static struct fb_fix_screeninfo da8xx_fb_fix = { |
| 184 | .id = "DA8xx FB Drv", |
| 185 | .type = FB_TYPE_PACKED_PIXELS, |
| 186 | .type_aux = 0, |
| 187 | .visual = FB_VISUAL_PSEUDOCOLOR, |
| 188 | .xpanstep = 0, |
| 189 | .ypanstep = 1, |
| 190 | .ywrapstep = 0, |
| 191 | .accel = FB_ACCEL_NONE |
| 192 | }; |
| 193 | |
| 194 | static const struct display_panel disp_panel = { |
| 195 | QVGA, |
| 196 | 16, |
| 197 | 16, |
| 198 | COLOR_ACTIVE, |
| 199 | }; |
| 200 | |
| 201 | static const struct lcd_ctrl_config lcd_cfg = { |
| 202 | &disp_panel, |
| 203 | .ac_bias = 255, |
| 204 | .ac_bias_intrpt = 0, |
| 205 | .dma_burst_sz = 16, |
| 206 | .bpp = 16, |
| 207 | .fdd = 255, |
| 208 | .tft_alt_mode = 0, |
| 209 | .stn_565_mode = 0, |
| 210 | .mono_8bit_mode = 0, |
| 211 | .invert_line_clock = 1, |
| 212 | .invert_frm_clock = 1, |
| 213 | .sync_edge = 0, |
| 214 | .sync_ctrl = 1, |
| 215 | .raster_order = 0, |
| 216 | }; |
| 217 | |
| 218 | /* Enable the Raster Engine of the LCD Controller */ |
| 219 | static inline void lcd_enable_raster(void) |
| 220 | { |
| 221 | u32 reg; |
| 222 | |
| 223 | reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); |
| 224 | if (!(reg & LCD_RASTER_ENABLE)) |
| 225 | lcdc_write(reg | LCD_RASTER_ENABLE, |
| 226 | &da8xx_fb_reg_base->raster_ctrl); |
| 227 | } |
| 228 | |
| 229 | /* Disable the Raster Engine of the LCD Controller */ |
| 230 | static inline void lcd_disable_raster(void) |
| 231 | { |
| 232 | u32 reg; |
| 233 | |
| 234 | reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); |
| 235 | if (reg & LCD_RASTER_ENABLE) |
| 236 | lcdc_write(reg & ~LCD_RASTER_ENABLE, |
| 237 | &da8xx_fb_reg_base->raster_ctrl); |
| 238 | } |
| 239 | |
| 240 | static void lcd_blit(int load_mode, struct da8xx_fb_par *par) |
| 241 | { |
| 242 | u32 start; |
| 243 | u32 end; |
| 244 | u32 reg_ras; |
| 245 | u32 reg_dma; |
| 246 | |
| 247 | /* init reg to clear PLM (loading mode) fields */ |
| 248 | reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); |
| 249 | reg_ras &= ~(3 << 20); |
| 250 | |
| 251 | reg_dma = lcdc_read(&da8xx_fb_reg_base->dma_ctrl); |
| 252 | |
| 253 | if (load_mode == LOAD_DATA) { |
| 254 | start = par->dma_start; |
| 255 | end = par->dma_end; |
| 256 | |
| 257 | reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY); |
| 258 | reg_dma |= LCD_END_OF_FRAME_INT_ENA; |
| 259 | |
| 260 | #if (LCD_NUM_BUFFERS == 2) |
| 261 | reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE; |
| 262 | lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); |
| 263 | lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); |
| 264 | lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); |
| 265 | lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); |
| 266 | #else |
| 267 | reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE; |
| 268 | lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); |
| 269 | lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); |
| 270 | lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); |
| 271 | lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); |
| 272 | #endif |
| 273 | |
| 274 | } else if (load_mode == LOAD_PALETTE) { |
| 275 | start = par->p_palette_base; |
| 276 | end = start + par->palette_sz - 1; |
| 277 | |
| 278 | reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY); |
| 279 | reg_ras |= LCD_PL_ENABLE; |
| 280 | |
| 281 | lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); |
| 282 | lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); |
| 283 | } |
| 284 | |
| 285 | lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl); |
| 286 | lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl); |
| 287 | |
| 288 | /* |
| 289 | * The Raster enable bit must be set after all other control fields are |
| 290 | * set. |
| 291 | */ |
| 292 | lcd_enable_raster(); |
| 293 | } |
| 294 | |
| 295 | /* Configure the Burst Size of DMA */ |
| 296 | static int lcd_cfg_dma(int burst_size) |
| 297 | { |
| 298 | u32 reg; |
| 299 | |
| 300 | reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001; |
| 301 | switch (burst_size) { |
| 302 | case 1: |
| 303 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1); |
| 304 | break; |
| 305 | case 2: |
| 306 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2); |
| 307 | break; |
| 308 | case 4: |
| 309 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4); |
| 310 | break; |
| 311 | case 8: |
| 312 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8); |
| 313 | break; |
| 314 | case 16: |
| 315 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16); |
| 316 | break; |
| 317 | default: |
| 318 | return -EINVAL; |
| 319 | } |
| 320 | lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl); |
| 321 | |
| 322 | return 0; |
| 323 | } |
| 324 | |
| 325 | static void lcd_cfg_ac_bias(int period, int transitions_per_int) |
| 326 | { |
| 327 | u32 reg; |
| 328 | |
| 329 | /* Set the AC Bias Period and Number of Transisitons per Interrupt */ |
| 330 | reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000; |
| 331 | reg |= LCD_AC_BIAS_FREQUENCY(period) | |
| 332 | LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int); |
| 333 | lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); |
| 334 | } |
| 335 | |
| 336 | static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width, |
| 337 | int front_porch) |
| 338 | { |
| 339 | u32 reg; |
| 340 | |
| 341 | reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf; |
| 342 | reg |= ((back_porch & 0xff) << 24) |
| 343 | | ((front_porch & 0xff) << 16) |
| 344 | | ((pulse_width & 0x3f) << 10); |
| 345 | lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0); |
| 346 | } |
| 347 | |
| 348 | static void lcd_cfg_vertical_sync(int back_porch, int pulse_width, |
| 349 | int front_porch) |
| 350 | { |
| 351 | u32 reg; |
| 352 | |
| 353 | reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff; |
| 354 | reg |= ((back_porch & 0xff) << 24) |
| 355 | | ((front_porch & 0xff) << 16) |
| 356 | | ((pulse_width & 0x3f) << 10); |
| 357 | lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1); |
| 358 | } |
| 359 | |
| 360 | static int lcd_cfg_display(const struct lcd_ctrl_config *cfg) |
| 361 | { |
| 362 | u32 reg; |
| 363 | |
| 364 | reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE | |
| 365 | LCD_MONO_8BIT_MODE | |
| 366 | LCD_MONOCHROME_MODE); |
| 367 | |
| 368 | switch (cfg->p_disp_panel->panel_shade) { |
| 369 | case MONOCHROME: |
| 370 | reg |= LCD_MONOCHROME_MODE; |
| 371 | if (cfg->mono_8bit_mode) |
| 372 | reg |= LCD_MONO_8BIT_MODE; |
| 373 | break; |
| 374 | case COLOR_ACTIVE: |
| 375 | reg |= LCD_TFT_MODE; |
| 376 | if (cfg->tft_alt_mode) |
| 377 | reg |= LCD_TFT_ALT_ENABLE; |
| 378 | break; |
| 379 | |
| 380 | case COLOR_PASSIVE: |
| 381 | if (cfg->stn_565_mode) |
| 382 | reg |= LCD_STN_565_ENABLE; |
| 383 | break; |
| 384 | |
| 385 | default: |
| 386 | return -EINVAL; |
| 387 | } |
| 388 | |
| 389 | /* enable additional interrupts here */ |
| 390 | reg |= LCD_UNDERFLOW_INT_ENA; |
| 391 | |
| 392 | lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl); |
| 393 | |
| 394 | reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2); |
| 395 | |
| 396 | if (cfg->sync_ctrl) |
| 397 | reg |= LCD_SYNC_CTRL; |
| 398 | else |
| 399 | reg &= ~LCD_SYNC_CTRL; |
| 400 | |
| 401 | if (cfg->sync_edge) |
| 402 | reg |= LCD_SYNC_EDGE; |
| 403 | else |
| 404 | reg &= ~LCD_SYNC_EDGE; |
| 405 | |
| 406 | if (cfg->invert_line_clock) |
| 407 | reg |= LCD_INVERT_LINE_CLOCK; |
| 408 | else |
| 409 | reg &= ~LCD_INVERT_LINE_CLOCK; |
| 410 | |
| 411 | if (cfg->invert_frm_clock) |
| 412 | reg |= LCD_INVERT_FRAME_CLOCK; |
| 413 | else |
| 414 | reg &= ~LCD_INVERT_FRAME_CLOCK; |
| 415 | |
| 416 | lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); |
| 417 | |
| 418 | return 0; |
| 419 | } |
| 420 | |
| 421 | static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, |
| 422 | u32 bpp, u32 raster_order) |
| 423 | { |
| 424 | u32 reg; |
| 425 | |
| 426 | /* Set the Panel Width */ |
| 427 | /* Pixels per line = (PPL + 1)*16 */ |
| 428 | /*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/ |
| 429 | width &= 0x3f0; |
| 430 | reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0); |
| 431 | reg &= 0xfffffc00; |
| 432 | reg |= ((width >> 4) - 1) << 4; |
| 433 | lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0); |
| 434 | |
| 435 | /* Set the Panel Height */ |
| 436 | reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1); |
| 437 | reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00); |
| 438 | lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1); |
| 439 | |
| 440 | /* Set the Raster Order of the Frame Buffer */ |
| 441 | reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8); |
| 442 | if (raster_order) |
| 443 | reg |= LCD_RASTER_ORDER; |
| 444 | lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl); |
| 445 | |
| 446 | switch (bpp) { |
| 447 | case 1: |
| 448 | case 2: |
| 449 | case 4: |
| 450 | case 16: |
| 451 | par->palette_sz = 16 * 2; |
| 452 | break; |
| 453 | |
| 454 | case 8: |
| 455 | par->palette_sz = 256 * 2; |
| 456 | break; |
| 457 | |
| 458 | default: |
| 459 | return -EINVAL; |
| 460 | } |
| 461 | |
| 462 | return 0; |
| 463 | } |
| 464 | |
| 465 | static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, |
| 466 | unsigned blue, unsigned transp, |
| 467 | struct fb_info *info) |
| 468 | { |
| 469 | struct da8xx_fb_par *par = info->par; |
| 470 | unsigned short *palette = (unsigned short *) par->v_palette_base; |
| 471 | u_short pal; |
| 472 | int update_hw = 0; |
| 473 | |
| 474 | if (regno > 255) |
| 475 | return 1; |
| 476 | |
| 477 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) |
| 478 | return 1; |
| 479 | |
| 480 | if (info->var.bits_per_pixel == 8) { |
| 481 | red >>= 4; |
| 482 | green >>= 8; |
| 483 | blue >>= 12; |
| 484 | |
| 485 | pal = (red & 0x0f00); |
| 486 | pal |= (green & 0x00f0); |
| 487 | pal |= (blue & 0x000f); |
| 488 | |
| 489 | if (palette[regno] != pal) { |
| 490 | update_hw = 1; |
| 491 | palette[regno] = pal; |
| 492 | } |
| 493 | } else if ((info->var.bits_per_pixel == 16) && regno < 16) { |
| 494 | red >>= (16 - info->var.red.length); |
| 495 | red <<= info->var.red.offset; |
| 496 | |
| 497 | green >>= (16 - info->var.green.length); |
| 498 | green <<= info->var.green.offset; |
| 499 | |
| 500 | blue >>= (16 - info->var.blue.length); |
| 501 | blue <<= info->var.blue.offset; |
| 502 | |
| 503 | par->pseudo_palette[regno] = red | green | blue; |
| 504 | |
| 505 | if (palette[0] != 0x4000) { |
| 506 | update_hw = 1; |
| 507 | palette[0] = 0x4000; |
| 508 | } |
| 509 | } |
| 510 | |
| 511 | /* Update the palette in the h/w as needed. */ |
| 512 | if (update_hw) |
| 513 | lcd_blit(LOAD_PALETTE, par); |
| 514 | |
| 515 | return 0; |
| 516 | } |
| 517 | |
| 518 | static void lcd_reset(struct da8xx_fb_par *par) |
| 519 | { |
| 520 | /* Disable the Raster if previously Enabled */ |
| 521 | lcd_disable_raster(); |
| 522 | |
| 523 | /* DMA has to be disabled */ |
| 524 | lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl); |
| 525 | lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl); |
| 526 | } |
| 527 | |
| 528 | static void lcd_calc_clk_divider(struct da8xx_fb_par *par) |
| 529 | { |
| 530 | unsigned int lcd_clk, div; |
| 531 | |
| 532 | /* Get clock from sysclk2 */ |
| 533 | lcd_clk = clk_get(2); |
| 534 | |
| 535 | div = lcd_clk / par->pxl_clk; |
| 536 | debug("LCD Clock: 0x%x Divider: 0x%x PixClk: 0x%x\n", |
| 537 | lcd_clk, div, par->pxl_clk); |
| 538 | |
| 539 | /* Configure the LCD clock divisor. */ |
| 540 | lcdc_write(LCD_CLK_DIVISOR(div) | |
| 541 | (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl); |
| 542 | } |
| 543 | |
| 544 | static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, |
| 545 | const struct da8xx_panel *panel) |
| 546 | { |
| 547 | u32 bpp; |
| 548 | int ret = 0; |
| 549 | |
| 550 | lcd_reset(par); |
| 551 | |
| 552 | /* Calculate the divider */ |
| 553 | lcd_calc_clk_divider(par); |
| 554 | |
| 555 | if (panel->invert_pxl_clk) |
| 556 | lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) | |
| 557 | LCD_INVERT_PIXEL_CLOCK), |
| 558 | &da8xx_fb_reg_base->raster_timing_2); |
| 559 | else |
| 560 | lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & |
| 561 | ~LCD_INVERT_PIXEL_CLOCK), |
| 562 | &da8xx_fb_reg_base->raster_timing_2); |
| 563 | |
| 564 | /* Configure the DMA burst size. */ |
| 565 | ret = lcd_cfg_dma(cfg->dma_burst_sz); |
| 566 | if (ret < 0) |
| 567 | return ret; |
| 568 | |
| 569 | /* Configure the AC bias properties. */ |
| 570 | lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt); |
| 571 | |
| 572 | /* Configure the vertical and horizontal sync properties. */ |
| 573 | lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp); |
| 574 | lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp); |
| 575 | |
| 576 | /* Configure for disply */ |
| 577 | ret = lcd_cfg_display(cfg); |
| 578 | if (ret < 0) |
| 579 | return ret; |
| 580 | |
| 581 | if (QVGA != cfg->p_disp_panel->panel_type) |
| 582 | return -EINVAL; |
| 583 | |
| 584 | if (cfg->bpp <= cfg->p_disp_panel->max_bpp && |
| 585 | cfg->bpp >= cfg->p_disp_panel->min_bpp) |
| 586 | bpp = cfg->bpp; |
| 587 | else |
| 588 | bpp = cfg->p_disp_panel->max_bpp; |
| 589 | if (bpp == 12) |
| 590 | bpp = 16; |
| 591 | ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width, |
| 592 | (unsigned int)panel->height, bpp, |
| 593 | cfg->raster_order); |
| 594 | if (ret < 0) |
| 595 | return ret; |
| 596 | |
| 597 | /* Configure FDD */ |
| 598 | lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) | |
| 599 | (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl); |
| 600 | |
| 601 | return 0; |
| 602 | } |
| 603 | |
| 604 | static void lcdc_dma_start(void) |
| 605 | { |
| 606 | struct da8xx_fb_par *par = da8xx_fb_info->par; |
| 607 | lcdc_write(par->dma_start, |
| 608 | &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); |
| 609 | lcdc_write(par->dma_end, |
| 610 | &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); |
| 611 | lcdc_write(0, |
| 612 | &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); |
| 613 | lcdc_write(0, |
| 614 | &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); |
| 615 | } |
| 616 | |
| 617 | static u32 lcdc_irq_handler(void) |
| 618 | { |
| 619 | struct da8xx_fb_par *par = da8xx_fb_info->par; |
| 620 | u32 stat = lcdc_read(&da8xx_fb_reg_base->stat); |
| 621 | u32 reg_ras; |
| 622 | |
| 623 | if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { |
| 624 | debug("LCD_SYNC_LOST\n"); |
| 625 | lcd_disable_raster(); |
| 626 | lcdc_write(stat, &da8xx_fb_reg_base->stat); |
| 627 | lcd_enable_raster(); |
| 628 | return LCD_SYNC_LOST; |
| 629 | } else if (stat & LCD_PL_LOAD_DONE) { |
| 630 | debug("LCD_PL_LOAD_DONE\n"); |
| 631 | /* |
| 632 | * Must disable raster before changing state of any control bit. |
| 633 | * And also must be disabled before clearing the PL loading |
| 634 | * interrupt via the following write to the status register. If |
| 635 | * this is done after then one gets multiple PL done interrupts. |
| 636 | */ |
| 637 | lcd_disable_raster(); |
| 638 | |
| 639 | lcdc_write(stat, &da8xx_fb_reg_base->stat); |
| 640 | |
| 641 | /* Disable PL completion inerrupt */ |
| 642 | reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); |
| 643 | reg_ras &= ~LCD_PL_ENABLE; |
| 644 | lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl); |
| 645 | |
| 646 | /* Setup and start data loading mode */ |
| 647 | lcd_blit(LOAD_DATA, par); |
| 648 | return LCD_PL_LOAD_DONE; |
| 649 | } else { |
| 650 | lcdc_write(stat, &da8xx_fb_reg_base->stat); |
| 651 | |
| 652 | if (stat & LCD_END_OF_FRAME0) |
| 653 | debug("LCD_END_OF_FRAME0\n"); |
| 654 | |
| 655 | lcdc_write(par->dma_start, |
| 656 | &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); |
| 657 | lcdc_write(par->dma_end, |
| 658 | &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); |
| 659 | par->vsync_flag = 1; |
| 660 | return LCD_END_OF_FRAME0; |
| 661 | } |
| 662 | return stat; |
| 663 | } |
| 664 | |
| 665 | static u32 wait_for_event(u32 event) |
| 666 | { |
| 667 | u32 timeout = 50000; |
| 668 | u32 ret; |
| 669 | |
| 670 | do { |
| 671 | ret = lcdc_irq_handler(); |
| 672 | udelay(1000); |
| 673 | } while (!(ret & event)); |
| 674 | |
| 675 | if (timeout <= 0) { |
| 676 | printf("%s: event %d not hit\n", __func__, event); |
| 677 | return -1; |
| 678 | } |
| 679 | |
| 680 | return 0; |
| 681 | |
| 682 | } |
| 683 | |
| 684 | void *video_hw_init(void) |
| 685 | { |
| 686 | struct da8xx_fb_par *par; |
Stefano Babic | 99a42ed | 2011-10-07 23:27:34 +0000 | [diff] [blame] | 687 | u32 size; |
| 688 | char *p; |
| 689 | |
| 690 | if (!lcd_panel) { |
| 691 | printf("Display not initialized\n"); |
| 692 | return NULL; |
| 693 | } |
| 694 | gpanel.winSizeX = lcd_panel->width; |
| 695 | gpanel.winSizeY = lcd_panel->height; |
| 696 | gpanel.plnSizeX = lcd_panel->width; |
| 697 | gpanel.plnSizeY = lcd_panel->height; |
| 698 | |
| 699 | switch (bits_x_pixel) { |
| 700 | case 24: |
| 701 | gpanel.gdfBytesPP = 4; |
| 702 | gpanel.gdfIndex = GDF_32BIT_X888RGB; |
| 703 | break; |
| 704 | case 16: |
| 705 | gpanel.gdfBytesPP = 2; |
| 706 | gpanel.gdfIndex = GDF_16BIT_565RGB; |
| 707 | break; |
| 708 | default: |
| 709 | gpanel.gdfBytesPP = 1; |
| 710 | gpanel.gdfIndex = GDF__8BIT_INDEX; |
| 711 | break; |
| 712 | } |
| 713 | |
| 714 | da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DAVINCI_LCD_CNTL_BASE; |
| 715 | |
| 716 | debug("Resolution: %dx%d %x\n", |
| 717 | gpanel.winSizeX, |
| 718 | gpanel.winSizeY, |
| 719 | lcd_cfg.bpp); |
| 720 | |
| 721 | size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par); |
| 722 | da8xx_fb_info = malloc(size); |
| 723 | debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info); |
| 724 | |
| 725 | if (!da8xx_fb_info) { |
| 726 | printf("Memory allocation failed for fb_info\n"); |
| 727 | return NULL; |
| 728 | } |
| 729 | memset(da8xx_fb_info, 0, size); |
| 730 | p = (char *)da8xx_fb_info; |
| 731 | da8xx_fb_info->par = p + sizeof(struct fb_info); |
| 732 | debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par); |
| 733 | |
| 734 | par = da8xx_fb_info->par; |
| 735 | par->pxl_clk = lcd_panel->pxl_clk; |
| 736 | |
| 737 | if (lcd_init(par, &lcd_cfg, lcd_panel) < 0) { |
| 738 | printf("lcd_init failed\n"); |
Stefano Babic | 99a42ed | 2011-10-07 23:27:34 +0000 | [diff] [blame] | 739 | goto err_release_fb; |
| 740 | } |
| 741 | |
| 742 | /* allocate frame buffer */ |
| 743 | par->vram_size = lcd_panel->width * lcd_panel->height * lcd_cfg.bpp; |
| 744 | par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8; |
| 745 | |
| 746 | par->vram_virt = malloc(par->vram_size); |
| 747 | |
| 748 | par->vram_phys = (dma_addr_t) par->vram_virt; |
| 749 | debug("Requesting 0x%x bytes for framebuffer at 0x%x\n", |
| 750 | (unsigned int)par->vram_size, |
| 751 | (unsigned int)par->vram_virt); |
| 752 | if (!par->vram_virt) { |
| 753 | printf("GLCD: malloc for frame buffer failed\n"); |
Stefano Babic | 99a42ed | 2011-10-07 23:27:34 +0000 | [diff] [blame] | 754 | goto err_release_fb; |
| 755 | } |
| 756 | |
| 757 | gpanel.frameAdrs = (unsigned int)par->vram_virt; |
| 758 | da8xx_fb_info->screen_base = (char *) par->vram_virt; |
| 759 | da8xx_fb_fix.smem_start = gpanel.frameAdrs; |
| 760 | da8xx_fb_fix.smem_len = par->vram_size; |
| 761 | da8xx_fb_fix.line_length = (lcd_panel->width * lcd_cfg.bpp) / 8; |
| 762 | |
| 763 | par->dma_start = par->vram_phys; |
| 764 | par->dma_end = par->dma_start + lcd_panel->height * |
| 765 | da8xx_fb_fix.line_length - 1; |
| 766 | |
| 767 | /* allocate palette buffer */ |
| 768 | par->v_palette_base = malloc(PALETTE_SIZE); |
| 769 | if (!par->v_palette_base) { |
| 770 | printf("GLCD: malloc for palette buffer failed\n"); |
| 771 | goto err_release_fb_mem; |
| 772 | } |
| 773 | memset(par->v_palette_base, 0, PALETTE_SIZE); |
| 774 | par->p_palette_base = (unsigned int)par->v_palette_base; |
| 775 | |
| 776 | /* Initialize par */ |
| 777 | da8xx_fb_info->var.bits_per_pixel = lcd_cfg.bpp; |
| 778 | |
| 779 | da8xx_fb_var.xres = lcd_panel->width; |
| 780 | da8xx_fb_var.xres_virtual = lcd_panel->width; |
| 781 | |
| 782 | da8xx_fb_var.yres = lcd_panel->height; |
| 783 | da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS; |
| 784 | |
| 785 | da8xx_fb_var.grayscale = |
| 786 | lcd_cfg.p_disp_panel->panel_shade == MONOCHROME ? 1 : 0; |
| 787 | da8xx_fb_var.bits_per_pixel = lcd_cfg.bpp; |
| 788 | |
| 789 | da8xx_fb_var.hsync_len = lcd_panel->hsw; |
| 790 | da8xx_fb_var.vsync_len = lcd_panel->vsw; |
| 791 | |
| 792 | /* Initialize fbinfo */ |
| 793 | da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT; |
| 794 | da8xx_fb_info->fix = da8xx_fb_fix; |
| 795 | da8xx_fb_info->var = da8xx_fb_var; |
| 796 | da8xx_fb_info->pseudo_palette = par->pseudo_palette; |
| 797 | da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ? |
| 798 | FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; |
| 799 | |
| 800 | /* Clear interrupt */ |
| 801 | memset((void *)par->vram_virt, 0, par->vram_size); |
| 802 | lcd_disable_raster(); |
| 803 | lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat); |
| 804 | debug("Palette at 0x%x size %d\n", par->p_palette_base, |
| 805 | par->palette_sz); |
| 806 | lcdc_dma_start(); |
| 807 | |
| 808 | /* Load a default palette */ |
| 809 | fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info); |
| 810 | |
| 811 | /* Check that the palette is loaded */ |
| 812 | wait_for_event(LCD_PL_LOAD_DONE); |
| 813 | |
| 814 | /* Wait until DMA is working */ |
| 815 | wait_for_event(LCD_END_OF_FRAME0); |
| 816 | |
| 817 | return (void *)&gpanel; |
| 818 | |
| 819 | err_release_fb_mem: |
| 820 | free(par->vram_virt); |
| 821 | |
| 822 | err_release_fb: |
| 823 | free(da8xx_fb_info); |
| 824 | |
| 825 | return NULL; |
| 826 | } |
| 827 | |
| 828 | void video_set_lut(unsigned int index, /* color number */ |
| 829 | unsigned char r, /* red */ |
| 830 | unsigned char g, /* green */ |
| 831 | unsigned char b /* blue */ |
| 832 | ) |
| 833 | { |
| 834 | |
| 835 | return; |
| 836 | } |
| 837 | |
| 838 | void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel) |
| 839 | { |
| 840 | lcd_panel = panel; |
| 841 | bits_x_pixel = bits_pixel; |
| 842 | } |