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git01.mediatek.com / filogic / uboot / 514628ce926c329c2e5736b7ed0ae590e1614da1 / . / arch / arm / mach-at91 / include / mach / at91_wdt.h
blob: 8ef8e007d7767308a5b46be46b02c51073723a41 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Jean-Christophe PLAGNIOL-VILLARDd5ee38e2009-03-27 23:26:42 +0100[diff] [blame]2/*
3 * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
4 *
5 * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
6 * Copyright (C) 2007 Andrew Victor
Prasanthi Chellakumar0509c4e2018-10-09 11:46:40 -0700[diff] [blame]7 * Copyright (C) 2018 Microchip Technology Inc.
Jean-Christophe PLAGNIOL-VILLARDd5ee38e2009-03-27 23:26:42 +0100[diff] [blame]8 *
9 * Watchdog Timer (WDT) - System peripherals regsters.
10 * Based on AT91SAM9261 datasheet revision D.
Jean-Christophe PLAGNIOL-VILLARDd5ee38e2009-03-27 23:26:42 +0100[diff] [blame]11 */
12
13#ifndef AT91_WDT_H
14#define AT91_WDT_H
15
Jens Scharsig698ad062010-02-03 22:46:01 +0100[diff] [blame]16#ifdef __ASSEMBLY__
17
Eric Benard8e518ec2011-06-06 22:48:26 +0000[diff] [blame]18#define AT91_ASM_WDT_MR (ATMEL_BASE_WDT + 0x04)
Jens Scharsig698ad062010-02-03 22:46:01 +0100[diff] [blame]19
20#else
21
22typedef struct at91_wdt {
23 u32 cr;
24 u32 mr;
25 u32 sr;
26} at91_wdt_t;
27
Stefan Roeseb9998fe2019-04-03 07:37:40 +0200[diff] [blame]28struct at91_wdt_priv {
29 void __iomem *regs;
30 u32 regval;
Stefan Roeseb9998fe2019-04-03 07:37:40 +0200[diff] [blame]31};
32
Jens Scharsig698ad062010-02-03 22:46:01 +0100[diff] [blame]33#endif
34
Prasanthi Chellakumar0509c4e2018-10-09 11:46:40 -0700[diff] [blame]35/* Watchdog Control Register */
36#define AT91_WDT_CR 0x00
Jens Scharsig698ad062010-02-03 22:46:01 +0100[diff] [blame]37#define AT91_WDT_CR_WDRSTT 1
38#define AT91_WDT_CR_KEY 0xa5000000 /* KEY Password */
39
Prasanthi Chellakumar0509c4e2018-10-09 11:46:40 -0700[diff] [blame]40/* Watchdog Mode Register*/
41#define AT91_WDT_MR 0X04
Jens Scharsig698ad062010-02-03 22:46:01 +0100[diff] [blame]42#define AT91_WDT_MR_WDV(x) (x & 0xfff)
43#define AT91_WDT_MR_WDFIEN 0x00001000
44#define AT91_WDT_MR_WDRSTEN 0x00002000
45#define AT91_WDT_MR_WDRPROC 0x00004000
46#define AT91_WDT_MR_WDDIS 0x00008000
47#define AT91_WDT_MR_WDD(x) ((x & 0xfff) << 16)
48#define AT91_WDT_MR_WDDBGHLT 0x10000000
49#define AT91_WDT_MR_WDIDLEHLT 0x20000000
50
Stefan Roeseb9998fe2019-04-03 07:37:40 +0200[diff] [blame]51/* Hardware timeout in seconds */
52#define WDT_MAX_TIMEOUT 16
Stefan Roeseb9998fe2019-04-03 07:37:40 +0200[diff] [blame]53
Jean-Christophe PLAGNIOL-VILLARDd5ee38e2009-03-27 23:26:42 +0100[diff] [blame]54#endif