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git01.mediatek.com / filogic / uboot / 513ee371ba5e52a8b0208aeb24f49d02d3e9081f / . / cpu / mcf5445x / start.S
blob: d64c5af0db8771c9ded63545822fc75998267204 [file] [log] [blame]
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]1/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <config.h>
25#include "version.h"
26
27#ifndef CONFIG_IDENT_STRING
28#define CONFIG_IDENT_STRING ""
29#endif
30
31/* last three long word reserved for cache status */
32#define CACR_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12)
33#define ICACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8)
34#define DCACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4)
35
36#define _START _start
37#define _FAULT _fault
38
39#define SAVE_ALL \
40 move.w #0x2700,%sr; /* disable intrs */ \
41 subl #60,%sp; /* space for 15 regs */ \
42 moveml %d0-%d7/%a0-%a6,%sp@;
43
44#define RESTORE_ALL \
45 moveml %sp@,%d0-%d7/%a0-%a6; \
46 addl #60,%sp; /* space for 15 regs */ \
47 rte;
48
49.text
50/*
51 * Vector table. This is used for initial platform startup.
52 * These vectors are to catch any un-intended traps.
53 */
54_vectors:
55
56INITSP: .long 0x00000000 /* Initial SP */
57INITPC: .long _START /* Initial PC */
58vector02: .long _FAULT /* Access Error */
59vector03: .long _FAULT /* Address Error */
60vector04: .long _FAULT /* Illegal Instruction */
61vector05: .long _FAULT /* Reserved */
62vector06: .long _FAULT /* Reserved */
63vector07: .long _FAULT /* Reserved */
64vector08: .long _FAULT /* Privilege Violation */
65vector09: .long _FAULT /* Trace */
66vector0A: .long _FAULT /* Unimplemented A-Line */
67vector0B: .long _FAULT /* Unimplemented F-Line */
68vector0C: .long _FAULT /* Debug Interrupt */
69vector0D: .long _FAULT /* Reserved */
70vector0E: .long _FAULT /* Format Error */
71vector0F: .long _FAULT /* Unitialized Int. */
72
73/* Reserved */
74vector10_17:
75.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
76
77vector18: .long _FAULT /* Spurious Interrupt */
78vector19: .long _FAULT /* Autovector Level 1 */
79vector1A: .long _FAULT /* Autovector Level 2 */
80vector1B: .long _FAULT /* Autovector Level 3 */
81vector1C: .long _FAULT /* Autovector Level 4 */
82vector1D: .long _FAULT /* Autovector Level 5 */
83vector1E: .long _FAULT /* Autovector Level 6 */
84vector1F: .long _FAULT /* Autovector Level 7 */
85
86/* TRAP #0 - #15 */
87vector20_2F:
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90
91/* Reserved */
92vector30_3F:
93.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
94.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
95
96vector64_127:
97.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
100.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
101.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
102.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
103.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
104.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
105
106vector128_191:
107.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
108.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
109.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
110.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
111.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
112.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
113.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
114.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
115
116vector192_255:
117.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
118.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
119.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
120.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
121.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
122.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
123.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
124.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
125
126 .text
127
128 .globl _start
129_start:
130 nop
131 nop
132 move.w #0x2700,%sr /* Mask off Interrupt */
133
134 /* Set vector base register at the beginning of the Flash */
135 move.l #CFG_FLASH_BASE, %d0
136 movec %d0, %VBR
137
138 move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
TsiChungLiew0573a7a2007-11-07 18:00:54 -0600[diff] [blame]139 movec %d0, %RAMBAR1
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]140
141 /* initialize general use internal ram */
142 move.l #0, %d0
143 move.l #(CACR_STATUS), %a1 /* CACR */
144 move.l #(ICACHE_STATUS), %a2 /* icache */
145 move.l #(DCACHE_STATUS), %a3 /* dcache */
146 move.l %d0, (%a1)
147 move.l %d0, (%a2)
148 move.l %d0, (%a3)
149
150 /* invalidate and disable cache */
151 move.l #0x01004100, %d0 /* Invalidate cache cmd */
152 movec %d0, %CACR /* Invalidate cache */
153 move.l #0, %d0
154 movec %d0, %ACR0
155 movec %d0, %ACR1
156 movec %d0, %ACR2
157 movec %d0, %ACR3
158
159 /* set stackpointer to end of internal ram to get some stackspace for
160 the first c-code */
161 move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
162 clr.l %sp@-
163
164 move.l #__got_start, %a5 /* put relocation table address to a5 */
165
166 bsr cpu_init_f /* run low-level CPU init code (from flash) */
167 bsr board_init_f /* run low-level board init code (from flash) */
168
169 /* board_init_f() does not return */
170
171/*------------------------------------------------------------------------------*/
172
173/*
174 * void relocate_code (addr_sp, gd, addr_moni)
175 *
176 * This "function" does not return, instead it continues in RAM
177 * after relocating the monitor code.
178 *
179 * r3 = dest
180 * r4 = src
181 * r5 = length in bytes
182 * r6 = cachelinesize
183 */
184 .globl relocate_code
185relocate_code:
186 link.w %a6,#0
187 move.l 8(%a6), %sp /* set new stack pointer */
188
189 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
190 move.l 16(%a6), %a0 /* Save copy of Destination Address */
191
192 move.l #CFG_MONITOR_BASE, %a1
193 move.l #__init_end, %a2
194 move.l %a0, %a3
195
196 /* copy the code to RAM */
1971:
198 move.l (%a1)+, (%a3)+
199 cmp.l %a1,%a2
200 bgt.s 1b
201
202/*
203 * We are done. Do not return, instead branch to second part of board
204 * initialization, now running from RAM.
205 */
206 move.l %a0, %a1
207 add.l #(in_ram - CFG_MONITOR_BASE), %a1
208 jmp (%a1)
209
210in_ram:
211
212clear_bss:
213 /*
214 * Now clear BSS segment
215 */
216 move.l %a0, %a1
217 add.l #(_sbss - CFG_MONITOR_BASE),%a1
218 move.l %a0, %d1
219 add.l #(_ebss - CFG_MONITOR_BASE),%d1
2206:
221 clr.l (%a1)+
222 cmp.l %a1,%d1
223 bgt.s 6b
224
225 /*
226 * fix got table in RAM
227 */
228 move.l %a0, %a1
229 add.l #(__got_start - CFG_MONITOR_BASE),%a1
230 move.l %a1,%a5 /* * fix got pointer register a5 */
231
232 move.l %a0, %a2
233 add.l #(__got_end - CFG_MONITOR_BASE),%a2
234
2357:
236 move.l (%a1),%d1
237 sub.l #_start,%d1
238 add.l %a0,%d1
239 move.l %d1,(%a1)+
240 cmp.l %a2, %a1
241 bne 7b
242
243 /* calculate relative jump to board_init_r in ram */
244 move.l %a0, %a1
245 add.l #(board_init_r - CFG_MONITOR_BASE), %a1
246
247 /* set parameters for board_init_r */
248 move.l %a0,-(%sp) /* dest_addr */
249 move.l %d0,-(%sp) /* gd */
250 jsr (%a1)
251
252/*------------------------------------------------------------------------------*/
253/* exception code */
254 .globl _fault
255_fault:
256 jmp _fault
257 .globl _exc_handler
258
259_exc_handler:
260 SAVE_ALL
261 movel %sp,%sp@-
262 bsr exc_handler
263 addql #4,%sp
264 RESTORE_ALL
265
266 .globl _int_handler
267_int_handler:
268 SAVE_ALL
269 movel %sp,%sp@-
270 bsr int_handler
271 addql #4,%sp
272 RESTORE_ALL
273
274/*------------------------------------------------------------------------------*/
275/* cache functions */
276 .globl icache_enable
277icache_enable:
278 move.l #(CACR_STATUS), %a1 /* read CACR Status */
279 move.l (%a1), %d1
280
281 move.l #0x00040100, %d0 /* Invalidate icache */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]282 movec %d0, %CACR
283
TsiChungLiew3b790502008-01-14 17:11:47 -0600[diff] [blame]284 move.l #(CFG_SDRAM_BASE + 0x1c000), %d0 /* Setup icache */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]285 movec %d0, %ACR2
286
TsiChungLiew3b790502008-01-14 17:11:47 -0600[diff] [blame]287 move.l #0x04088020, %d0 /* Enable bcache and icache */
288 movec %d0, %CACR
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]289
290 move.l #(ICACHE_STATUS), %a1
291 moveq #1, %d0
292 move.l %d0, (%a1)
293 rts
294
295 .globl icache_disable
296icache_disable:
297 move.l #(CACR_STATUS), %a1 /* read CACR Status */
298 move.l (%a1), %d0
299
TsiChungLiew3b790502008-01-14 17:11:47 -0600[diff] [blame]300 move.l #0xFFF77BFF, %d0
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]301 or.l #0x00040100, %d0 /* Setup cache mask */
302 movec %d0, %CACR /* Invalidate icache */
303 clr.l %d0
304 movec %d0, %ACR2
305 movec %d0, %ACR3
306
307 move.l #(ICACHE_STATUS), %a1
308 moveq #0, %d0
309 move.l %d0, (%a1)
310 rts
311
312 .globl icache_status
313icache_status:
314 move.l #(ICACHE_STATUS), %a1
315 move.l (%a1), %d0
316 rts
317
318 .globl icache_invalid
319icache_invalid:
320 move.l #(CACR_STATUS), %a1 /* read CACR Status */
321 move.l (%a1), %d0
322
TsiChungLiew3b790502008-01-14 17:11:47 -0600[diff] [blame]323 move.l #0x00040100, %d0 /* Invalidate icache */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]324 movec %d0, %CACR /* Enable and invalidate cache */
325 rts
326
327 .globl dcache_enable
328dcache_enable:
329 move.l #(CACR_STATUS), %a1 /* read CACR Status */
330 move.l (%a1), %d1
331
TsiChungLiew3b790502008-01-14 17:11:47 -0600[diff] [blame]332 move.l #0x01040100, %d0
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]333 movec %d0, %CACR /* Invalidate dcache */
334
TsiChungLiew3b790502008-01-14 17:11:47 -0600[diff] [blame]335 move.l #0x80088020, %d0 /* Enable bcache and icache */
336 movec %d0, %CACR
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]337
338 move.l #(DCACHE_STATUS), %a1
339 moveq #1, %d0
340 move.l %d0, (%a1)
341 rts
342
343 .globl dcache_disable
344dcache_disable:
345 move.l #(CACR_STATUS), %a1 /* read CACR Status */
346 move.l (%a1), %d0
347
348 and.l #0x7FFFFFFF, %d0
349 or.l #0x01000000, %d0 /* Setup cache mask */
350 movec %d0, %CACR /* Disable dcache */
351 clr.l %d0
352 movec %d0, %ACR0
353 movec %d0, %ACR1
354
355 move.l #(DCACHE_STATUS), %a1
356 moveq #0, %d0
357 move.l %d0, (%a1)
358 rts
359
360 .globl dcache_invalid
361dcache_invalid:
362 move.l #(CACR_STATUS), %a1 /* read CACR Status */
363 move.l (%a1), %d0
364
TsiChungLiew3b790502008-01-14 17:11:47 -0600[diff] [blame]365 move.l #0x81088020, %d0 /* Setup cache mask */
TsiChungLiewfc3ca3b62007-08-16 15:05:11 -0500[diff] [blame]366 movec %d0, %CACR /* Enable and invalidate cache */
367 rts
368
369 .globl dcache_status
370dcache_status:
371 move.l #(DCACHE_STATUS), %a1
372 move.l (%a1), %d0
373 rts
374
375/*------------------------------------------------------------------------------*/
376
377 .globl version_string
378version_string:
379 .ascii U_BOOT_VERSION
380 .ascii " (", __DATE__, " - ", __TIME__, ")"
381 .ascii CONFIG_IDENT_STRING, "\0"