| Aubrey Li | 51185db | 2007-03-20 18:16:24 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c |
| 3 | * |
| 4 | * This file is subject to the terms and conditions of the GNU General Public |
| 5 | * License. See the file COPYING in the main directory of this archive |
| 6 | * for more details. |
| 7 | * |
| 8 | * Changed by HuTao Apr18, 2003 |
| 9 | * |
| 10 | * Copyright was missing when I got the code so took from MIPS arch ...MaTed--- |
| 11 | * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle |
| 12 | * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle |
| 13 | * |
| 14 | * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca> |
| 15 | * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com) |
| 16 | * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com> |
| 17 | * |
| 18 | * Adapted for BlackFin BF533 by Bas Vermeulen <bas@buyways.nl> |
| 19 | * Copyright (c) 2003 BuyWays B.V. (www.buyways.nl) |
| 20 | * Copyright (c) 2004 LG Soft India. |
| 21 | * Copyright (c) 2004 HHTech. |
| 22 | * |
| 23 | * Adapted for BlackFin BF561 by Bas Vermeulen <bas@buyways.nl> |
| 24 | * Copyright (c) 2005 BuyWays B.V. (www.buyways.nl) |
| 25 | */ |
| 26 | |
| 27 | #ifndef _BF561_IRQ_H_ |
| 28 | #define _BF561_IRQ_H_ |
| 29 | |
| 30 | /* |
| 31 | * Interrupt source definitions: |
| 32 | * Event Source Core Event Name IRQ No |
| 33 | * Emulation Events EMU 0 |
| 34 | * Reset RST 1 |
| 35 | * NMI NMI 2 |
| 36 | * Exception EVX 3 |
| 37 | * Reserved -- 4 |
| 38 | * Hardware Error IVHW 5 |
| 39 | * Core Timer IVTMR 6 |
| 40 | * |
| 41 | * PLL Wakeup Interrupt IVG7 7 |
| 42 | * DMA1 Error (generic) IVG7 8 |
| 43 | * DMA2 Error (generic) IVG7 9 |
| 44 | * IMDMA Error (generic) IVG7 10 |
| 45 | * PPI1 Error Interrupt IVG7 11 |
| 46 | * PPI2 Error Interrupt IVG7 12 |
| 47 | * SPORT0 Error Interrupt IVG7 13 |
| 48 | * SPORT1 Error Interrupt IVG7 14 |
| 49 | * SPI Error Interrupt IVG7 15 |
| 50 | * UART Error Interrupt IVG7 16 |
| 51 | * Reserved Interrupt IVG7 17 |
| 52 | * |
| 53 | * DMA1 0 Interrupt(PPI1) IVG8 18 |
| 54 | * DMA1 1 Interrupt(PPI2) IVG8 19 |
| 55 | * DMA1 2 Interrupt IVG8 20 |
| 56 | * DMA1 3 Interrupt IVG8 21 |
| 57 | * DMA1 4 Interrupt IVG8 22 |
| 58 | * DMA1 5 Interrupt IVG8 23 |
| 59 | * DMA1 6 Interrupt IVG8 24 |
| 60 | * DMA1 7 Interrupt IVG8 25 |
| 61 | * DMA1 8 Interrupt IVG8 26 |
| 62 | * DMA1 9 Interrupt IVG8 27 |
| 63 | * DMA1 10 Interrupt IVG8 28 |
| 64 | * DMA1 11 Interrupt IVG8 29 |
| 65 | * |
| 66 | * DMA2 0 (SPORT0 RX) IVG9 30 |
| 67 | * DMA2 1 (SPORT0 TX) IVG9 31 |
| 68 | * DMA2 2 (SPORT1 RX) IVG9 32 |
| 69 | * DMA2 3 (SPORT2 TX) IVG9 33 |
| 70 | * DMA2 4 (SPI) IVG9 34 |
| 71 | * DMA2 5 (UART RX) IVG9 35 |
| 72 | * DMA2 6 (UART TX) IVG9 36 |
| 73 | * DMA2 7 Interrupt IVG9 37 |
| 74 | * DMA2 8 Interrupt IVG9 38 |
| 75 | * DMA2 9 Interrupt IVG9 39 |
| 76 | * DMA2 10 Interrupt IVG9 40 |
| 77 | * DMA2 11 Interrupt IVG9 41 |
| 78 | * |
| 79 | * TIMER 0 Interrupt IVG10 42 |
| 80 | * TIMER 1 Interrupt IVG10 43 |
| 81 | * TIMER 2 Interrupt IVG10 44 |
| 82 | * TIMER 3 Interrupt IVG10 45 |
| 83 | * TIMER 4 Interrupt IVG10 46 |
| 84 | * TIMER 5 Interrupt IVG10 47 |
| 85 | * TIMER 6 Interrupt IVG10 48 |
| 86 | * TIMER 7 Interrupt IVG10 49 |
| 87 | * TIMER 8 Interrupt IVG10 50 |
| 88 | * TIMER 9 Interrupt IVG10 51 |
| 89 | * TIMER 10 Interrupt IVG10 52 |
| 90 | * TIMER 11 Interrupt IVG10 53 |
| 91 | * |
| 92 | * Programmable Flags0 A (8) IVG11 54 |
| 93 | * Programmable Flags0 B (8) IVG11 55 |
| 94 | * Programmable Flags1 A (8) IVG11 56 |
| 95 | * Programmable Flags1 B (8) IVG11 57 |
| 96 | * Programmable Flags2 A (8) IVG11 58 |
| 97 | * Programmable Flags2 B (8) IVG11 59 |
| 98 | * |
| 99 | * MDMA1 0 write/read INT IVG8 60 |
| 100 | * MDMA1 1 write/read INT IVG8 61 |
| 101 | * |
| 102 | * MDMA2 0 write/read INT IVG9 62 |
| 103 | * MDMA2 1 write/read INT IVG9 63 |
| 104 | * |
| 105 | * IMDMA 0 write/read INT IVG12 64 |
| 106 | * IMDMA 1 write/read INT IVG12 65 |
| 107 | * |
| 108 | * Watch Dog Timer IVG13 66 |
| 109 | * |
| 110 | * Reserved interrupt IVG7 67 |
| 111 | * Reserved interrupt IVG7 68 |
| 112 | * Supplemental interrupt 0 IVG7 69 |
| 113 | * supplemental interrupt 1 IVG7 70 |
| 114 | * |
| 115 | * Software Interrupt 1 IVG14 71 |
| 116 | * Software Interrupt 2 IVG15 72 |
| 117 | */ |
| 118 | |
| 119 | /* |
| 120 | * The ABSTRACT IRQ definitions |
| 121 | * the first seven of the following are fixed, |
| 122 | * the rest you change if you need to. |
| 123 | */ |
| 124 | /* IVG 0-6 */ |
| 125 | #define IRQ_EMU 0 /* Emulation */ |
| 126 | #define IRQ_RST 1 /* Reset */ |
| 127 | #define IRQ_NMI 2 /* Non Maskable Interrupt */ |
| 128 | #define IRQ_EVX 3 /* Exception */ |
| 129 | #define IRQ_UNUSED 4 /* Reserved interrupt */ |
| 130 | #define IRQ_HWERR 5 /* Hardware Error */ |
| 131 | #define IRQ_CORETMR 6 /* Core timer */ |
| 132 | |
| 133 | #define IRQ_UART_RX_BIT 0x10000000 |
| 134 | #define IRQ_UART_TX_BIT 0x20000000 |
| 135 | #define IRQ_UART_ERROR_BIT 0x200 |
| 136 | |
| 137 | #endif /* _BF561_IRQ_H_ */ |