Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 51144c992f20a4c3e8cd393197551ac16230efa3 / . / include / configs / hsdk-4xd.h
blob: 09fbbe90f1bb5c6569a9f63a9decf802ddbd198b [file] [log] [blame]
Eugeniy Paltsevc9a721f2020-04-22 02:59:31 +0300[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2020 Synopsys, Inc. All rights reserved.
4 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
5 */
6
7#ifndef _CONFIG_HSDK_H_
8#define _CONFIG_HSDK_H_
9
10#include <linux/sizes.h>
11
12/*
13 * CPU configuration
14 */
15#define NR_CPUS 4
16#define ARC_PERIPHERAL_BASE 0xF0000000
17#define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000)
18#define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000)
19
20/*
21 * Memory configuration
22 */
23#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
24
25#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
26#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
27#define CONFIG_SYS_SDRAM_SIZE SZ_1G
28
29#define CONFIG_SYS_INIT_SP_ADDR \
30 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
31
Eugeniy Paltsevc9a721f2020-04-22 02:59:31 +0300[diff] [blame]32#define CONFIG_SYS_BOOTM_LEN SZ_128M
Eugeniy Paltsevc9a721f2020-04-22 02:59:31 +0300[diff] [blame]33
34/*
35 * UART configuration
36 */
37#define CONFIG_SYS_NS16550_SERIAL
38#define CONFIG_SYS_NS16550_CLK 33330000
39#define CONFIG_SYS_NS16550_MEM32
40
41/*
42 * Ethernet PHY configuration
43 */
44
45/*
46 * USB 1.1 configuration
47 */
48#define CONFIG_USB_OHCI_NEW
49#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
50
51/*
52 * Environment settings
53 */
54#define CONFIG_EXTRA_ENV_SETTINGS \
55 "upgrade=if mmc rescan && " \
56 "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \
57 "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \
58 "\"Fail to upgrade.\n" \
59 "Do you have u-boot-update.scr and u-boot.head on first (FAT) SD card partition?\"" \
60 "; fi\0" \
61 "core_mask=0xF\0" \
62 "hsdk_hs45d=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
63setenv l2_cache_ena 0x0; setenv icache_ena 0x0; setenv csm_location 0x10; \
64setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
65setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
66 "hsdk_hs47d=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
67setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
68setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
69setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
70 "hsdk_hs47d_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
71setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
72setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
73setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
74 "hsdk_hs48=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
75setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
76setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
77setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
78 "hsdk_hs48_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
79setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
80setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
81setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
82 "hsdk_hs48x2=run hsdk_hs47dx2;\0" \
83 "hsdk_hs47dx2=setenv core_mask 0x3; setenv haps_apb_location 0x1; \
84setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
85setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
86setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
87setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \
88 "hsdk_hs48x3=run hsdk_hs47dx3;\0" \
89 "hsdk_hs47dx3=setenv core_mask 0x7; setenv haps_apb_location 0x1; \
90setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
91setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
92setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
93setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
94setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \
95 "hsdk_hs48x4=run hsdk_hs47dx4;\0" \
96 "hsdk_hs47dx4=setenv core_mask 0xF; setenv haps_apb_location 0x1; \
97setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
98setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
99setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
100setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
101setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \
102setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
103
104/*
105 * Environment configuration
106 */
Eugeniy Paltsevc9a721f2020-04-22 02:59:31 +0300[diff] [blame]107
108/* Cli configuration */
109#define CONFIG_SYS_CBSIZE SZ_2K
110
111/*
112 * Callback configuration
113 */
Eugeniy Paltsevc9a721f2020-04-22 02:59:31 +0300[diff] [blame]114
115#endif /* _CONFIG_HSDK_H_ */