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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Simon Glass45be32c2014-12-10 08:55:51 -07002/*
3 * Test-related constants for sandbox
4 *
5 * Copyright (c) 2014 Google, Inc
Simon Glass45be32c2014-12-10 08:55:51 -07006 */
7
8#ifndef __ASM_TEST_H
9#define __ASM_TEST_H
10
11/* The sandbox driver always permits an I2C device with this address */
Simon Glass70778bc2015-03-05 12:25:26 -070012#define SANDBOX_I2C_TEST_ADDR 0x59
13
14#define SANDBOX_PCI_VENDOR_ID 0x1234
Simon Glass21c8f1a2019-09-25 08:56:01 -060015#define SANDBOX_PCI_SWAP_CASE_EMUL_ID 0x5678
Simon Glass8c501022019-12-06 21:41:54 -070016#define SANDBOX_PCI_PMC_EMUL_ID 0x5677
Simon Glass937bb472019-12-06 21:41:57 -070017#define SANDBOX_PCI_P2SB_EMUL_ID 0x5676
Simon Glass70778bc2015-03-05 12:25:26 -070018#define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM
19#define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL
Simon Glass45be32c2014-12-10 08:55:51 -070020
Bin Mengd74d3122018-08-03 01:14:53 -070021#define PCI_CAP_ID_PM_OFFSET 0x50
22#define PCI_CAP_ID_EXP_OFFSET 0x60
23#define PCI_CAP_ID_MSIX_OFFSET 0x70
Alex Margineanf1274432019-06-07 11:24:24 +030024#define PCI_CAP_ID_EA_OFFSET 0x80
Bin Mengd74d3122018-08-03 01:14:53 -070025
26#define PCI_EXT_CAP_ID_ERR_OFFSET 0x100
27#define PCI_EXT_CAP_ID_VC_OFFSET 0x200
28#define PCI_EXT_CAP_ID_DSN_OFFSET 0x300
29
Bin Mengc69ae412018-08-03 01:14:46 -070030/* Useful for PCI_VDEVICE() macro */
31#define PCI_VENDOR_ID_SANDBOX SANDBOX_PCI_VENDOR_ID
32#define SWAP_CASE_DRV_DATA 0x55aa
33
Simon Glass8cc4d822015-07-06 12:54:24 -060034#define SANDBOX_CLK_RATE 32768
35
Alex Margineanf1274432019-06-07 11:24:24 +030036/* Macros used to test PCI EA capability structure */
37#define PCI_CAP_EA_BASE_LO0 0x00100000
38#define PCI_CAP_EA_BASE_LO1 0x00110000
39#define PCI_CAP_EA_BASE_LO2 0x00120000
40#define PCI_CAP_EA_BASE_LO4 0x00140000
41#define PCI_CAP_EA_BASE_HI2 0x00020000ULL
42#define PCI_CAP_EA_BASE_HI4 0x00040000ULL
43#define PCI_CAP_EA_SIZE_LO 0x0000ffff
44#define PCI_CAP_EA_SIZE_HI 0x00000010ULL
45#define PCI_EA_BAR2_MAGIC 0x72727272
46#define PCI_EA_BAR4_MAGIC 0x74747474
47
Simon Glasscd556522015-07-06 12:54:35 -060048/* System controller driver data */
49enum {
50 SYSCON0 = 32,
51 SYSCON1,
52
53 SYSCON_COUNT
54};
55
Simon Glass4c70ed92015-04-20 12:37:15 -060056/**
57 * sandbox_i2c_set_test_mode() - set test mode for running unit tests
58 *
59 * See sandbox_i2c_xfer() for the behaviour changes.
60 *
61 * @bus: sandbox I2C bus to adjust
62 * @test_mode: true to select test mode, false to run normally
63 */
64void sandbox_i2c_set_test_mode(struct udevice *bus, bool test_mode);
65
Simon Glass45be32c2014-12-10 08:55:51 -070066enum sandbox_i2c_eeprom_test_mode {
67 SIE_TEST_MODE_NONE,
68 /* Permits read/write of only one byte per I2C transaction */
69 SIE_TEST_MODE_SINGLE_BYTE,
70};
71
72void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev,
73 enum sandbox_i2c_eeprom_test_mode mode);
74
75void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len);
76
Robert Beckettf695f6e2019-10-28 17:44:59 +000077void sandbox_i2c_eeprom_set_chip_addr_offset_mask(struct udevice *dev,
78 uint mask);
79
Robert Beckett1fe8a492019-10-28 17:44:58 +000080uint sanbox_i2c_eeprom_get_prev_addr(struct udevice *dev);
81
82uint sanbox_i2c_eeprom_get_prev_offset(struct udevice *dev);
83
Simon Glassc404aa62015-04-20 12:37:24 -060084/**
85 * sandbox_i2c_rtc_set_offset() - set the time offset from system/base time
86 *
87 * @dev: RTC device to adjust
88 * @use_system_time: true to use system time, false to use @base_time
89 * @offset: RTC offset from current system/base time (-1 for no
90 * change)
91 * @return old value of RTC offset
92 */
93long sandbox_i2c_rtc_set_offset(struct udevice *dev, bool use_system_time,
94 int offset);
95
96/**
97 * sandbox_i2c_rtc_get_set_base_time() - get and set the base time
98 *
99 * @dev: RTC device to adjust
100 * @base_time: New base system time (set to -1 for no change)
101 * @return old base time
102 */
103long sandbox_i2c_rtc_get_set_base_time(struct udevice *dev, long base_time);
104
Simon Glassbe4ebd12015-11-08 23:48:06 -0700105int sandbox_usb_keyb_add_string(struct udevice *dev, const char *str);
106
Mario Six02ad6fb2018-09-27 09:19:31 +0200107/**
108 * sandbox_osd_get_mem() - get the internal memory of a sandbox OSD
109 *
110 * @dev: OSD device for which to access the internal memory for
111 * @buf: pointer to buffer to receive the OSD memory data
112 * @buflen: length of buffer in bytes
113 */
114int sandbox_osd_get_mem(struct udevice *dev, u8 *buf, size_t buflen);
Simon Glass5620cf82018-10-01 12:22:40 -0600115
116/**
117 * sandbox_pwm_get_config() - get the PWM config for a channel
118 *
119 * @dev: Device to check
120 * @channel: Channel number to check
121 * @period_ns: Period of the PWM in nanoseconds
122 * @duty_ns: Current duty cycle of the PWM in nanoseconds
123 * @enable: true if the PWM is enabled
124 * @polarity: true if the PWM polarity is active high
125 * @return 0 if OK, -ENOSPC if the PWM number is invalid
126 */
127int sandbox_pwm_get_config(struct udevice *dev, uint channel, uint *period_nsp,
128 uint *duty_nsp, bool *enablep, bool *polarityp);
129
Simon Glass36eee8c2018-11-06 15:21:41 -0700130/**
131 * sandbox_sf_set_block_protect() - Set the BP bits of the status register
132 *
133 * @dev: Device to update
134 * @bp_mask: BP bits to set (bits 2:0, so a value of 0 to 7)
135 */
136void sandbox_sf_set_block_protect(struct udevice *dev, int bp_mask);
137
Simon Glassed96cde2018-12-10 10:37:33 -0700138/**
139 * sandbox_get_codec_params() - Read back codec parameters
140 *
141 * This reads back the parameters set by audio_codec_set_params() for the
142 * sandbox audio driver. Arguments are as for that function.
143 */
144void sandbox_get_codec_params(struct udevice *dev, int *interfacep, int *ratep,
145 int *mclk_freqp, int *bits_per_samplep,
146 uint *channelsp);
147
Simon Glassc953aaf2018-12-10 10:37:34 -0700148/**
149 * sandbox_get_i2s_sum() - Read back the sum of the audio data so far
150 *
151 * This data is provided to the sandbox driver by the I2S tx_data() method.
152 *
153 * @dev: Device to check
154 * @return sum of audio data
155 */
156int sandbox_get_i2s_sum(struct udevice *dev);
157
Simon Glass76072ac2018-12-10 10:37:36 -0700158/**
159 * sandbox_get_setup_called() - Returns the number of times setup(*) was called
160 *
161 * This is used in the sound test
162 *
163 * @dev: Device to check
164 * @return call count for the setup() method
165 */
166int sandbox_get_setup_called(struct udevice *dev);
167
168/**
169 * sandbox_get_sound_sum() - Read back the sum of the sound data so far
170 *
171 * This data is provided to the sandbox driver by the sound play() method.
172 *
173 * @dev: Device to check
174 * @return sum of audio data
175 */
176int sandbox_get_sound_sum(struct udevice *dev);
177
Simon Glass53a68b32019-02-16 20:24:50 -0700178/**
Simon Glassecd02e72019-02-16 20:24:54 -0700179 * sandbox_set_allow_beep() - Set whether the 'beep' interface is supported
180 *
181 * @dev: Device to update
182 * @allow: true to allow the start_beep() method, false to disallow it
183 */
184void sandbox_set_allow_beep(struct udevice *dev, bool allow);
185
186/**
187 * sandbox_get_beep_frequency() - Get the frequency of the current beep
188 *
189 * @dev: Device to check
190 * @return frequency of beep, if there is an active beep, else 0
191 */
192int sandbox_get_beep_frequency(struct udevice *dev);
193
194/**
Simon Glass53a68b32019-02-16 20:24:50 -0700195 * sandbox_get_pch_spi_protect() - Get the PCI SPI protection status
196 *
197 * @dev: Device to check
198 * @return 0 if not protected, 1 if protected
199 */
200int sandbox_get_pch_spi_protect(struct udevice *dev);
201
Ramon Friedafdb3422019-04-27 11:15:24 +0300202/**
203 * sandbox_get_pci_ep_irq_count() - Get the PCI EP IRQ count
204 *
205 * @dev: Device to check
206 * @return irq count
207 */
208int sandbox_get_pci_ep_irq_count(struct udevice *dev);
209
Simon Glass72231f72019-09-25 08:56:42 -0600210/**
211 * sandbox_pci_read_bar() - Read the BAR value for a read_config operation
212 *
213 * This is used in PCI emulators to read a base address reset. This has special
214 * rules because when the register is set to 0xffffffff it can be used to
215 * discover the type and size of the BAR.
216 *
217 * @barval: Current value of the BAR
218 * @type: Type of BAR (PCI_BASE_ADDRESS_SPACE_IO or
219 * PCI_BASE_ADDRESS_MEM_TYPE_32)
220 * @size: Size of BAR in bytes
221 * @return BAR value to return from emulator
222 */
223uint sandbox_pci_read_bar(u32 barval, int type, uint size);
224
Simon Glassc667fb02019-10-11 16:16:48 -0600225/**
226 * sandbox_set_enable_memio() - Enable readl/writel() for sandbox
227 *
228 * Normally these I/O functions do nothing with sandbox. Certain tests need them
229 * to work as for other architectures, so this function can be used to enable
230 * them.
231 *
232 * @enable: true to enable, false to disable
233 */
234void sandbox_set_enable_memio(bool enable);
235
Simon Glass45be32c2014-12-10 08:55:51 -0700236#endif