blob: 0133eaa2ca9fc9ce2bb33db1d1e8c017e04c6517 [file] [log] [blame]
wdenk4ca32362004-12-16 15:52:40 +00001/*
2 * (C) Copyright 2004
3 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk4ca32362004-12-16 15:52:40 +00006 */
7
Marian Balakowicz209d5132007-11-15 13:29:55 +01008#define SDRAM_DDR 0 /* is SDR */
wdenk4ca32362004-12-16 15:52:40 +00009
wdenk4ca32362004-12-16 15:52:40 +000010/* Settings for XLB = 132 MHz */
11#define SDRAM_MODE 0x00CD0000
wdenk4ca32362004-12-16 15:52:40 +000012#define SDRAM_CONTROL 0x504F0000
13#define SDRAM_CONFIG1 0xD2322800
wdenk4ca32362004-12-16 15:52:40 +000014#define SDRAM_CONFIG2 0x8AD70000