Andy Fleming | 71706df | 2007-04-23 02:54:25 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007 Freescale Semiconductor. |
| 3 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Andy Fleming | 71706df | 2007-04-23 02:54:25 -0500 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Anton Vorontsov | 734b442 | 2007-10-22 18:12:46 +0400 | [diff] [blame] | 8 | #include <asm/io.h> |
| 9 | |
Andy Fleming | 71706df | 2007-04-23 02:54:25 -0500 | [diff] [blame] | 10 | #include "bcsr.h" |
| 11 | |
Kim Phillips | 402673f | 2012-10-29 13:34:38 +0000 | [diff] [blame] | 12 | void enable_8568mds_duart(void) |
Andy Fleming | 71706df | 2007-04-23 02:54:25 -0500 | [diff] [blame] | 13 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 14 | volatile uint* duart_mux = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0060); |
| 15 | volatile uint* devices = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0070); |
| 16 | volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); |
Andy Fleming | 71706df | 2007-04-23 02:54:25 -0500 | [diff] [blame] | 17 | |
| 18 | *duart_mux = 0x80000000; /* Set the mux to Duart on PMUXCR */ |
| 19 | *devices = 0; /* Enable all peripheral devices */ |
| 20 | bcsr[5] |= 0x01; /* Enable Duart in BCSR*/ |
| 21 | } |
| 22 | |
Kim Phillips | 402673f | 2012-10-29 13:34:38 +0000 | [diff] [blame] | 23 | void enable_8568mds_flash_write(void) |
Andy Fleming | 71706df | 2007-04-23 02:54:25 -0500 | [diff] [blame] | 24 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 25 | volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); |
Andy Fleming | 71706df | 2007-04-23 02:54:25 -0500 | [diff] [blame] | 26 | |
| 27 | bcsr[9] |= 0x01; |
| 28 | } |
| 29 | |
Kim Phillips | 402673f | 2012-10-29 13:34:38 +0000 | [diff] [blame] | 30 | void disable_8568mds_flash_write(void) |
Andy Fleming | 71706df | 2007-04-23 02:54:25 -0500 | [diff] [blame] | 31 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 32 | volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); |
Andy Fleming | 71706df | 2007-04-23 02:54:25 -0500 | [diff] [blame] | 33 | |
| 34 | bcsr[9] &= ~(0x01); |
| 35 | } |
Andy Fleming | ee0e917 | 2007-08-14 00:14:25 -0500 | [diff] [blame] | 36 | |
Kim Phillips | 402673f | 2012-10-29 13:34:38 +0000 | [diff] [blame] | 37 | void enable_8568mds_qe_mdio(void) |
Andy Fleming | ee0e917 | 2007-08-14 00:14:25 -0500 | [diff] [blame] | 38 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 39 | u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); |
Andy Fleming | ee0e917 | 2007-08-14 00:14:25 -0500 | [diff] [blame] | 40 | |
| 41 | bcsr[7] |= 0x01; |
| 42 | } |
Anton Vorontsov | 734b442 | 2007-10-22 18:12:46 +0400 | [diff] [blame] | 43 | |
| 44 | #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) |
| 45 | void reset_8568mds_uccs(void) |
| 46 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 47 | volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); |
Anton Vorontsov | 734b442 | 2007-10-22 18:12:46 +0400 | [diff] [blame] | 48 | |
| 49 | /* Turn off UCC1 & UCC2 */ |
| 50 | out_8(&bcsr[8], in_8(&bcsr[8]) & ~BCSR_UCC1_GETH_EN); |
| 51 | out_8(&bcsr[9], in_8(&bcsr[9]) & ~BCSR_UCC2_GETH_EN); |
| 52 | |
| 53 | /* Mode is RGMII, all bits clear */ |
| 54 | out_8(&bcsr[11], in_8(&bcsr[11]) & ~(BCSR_UCC1_MODE_MSK | |
| 55 | BCSR_UCC2_MODE_MSK)); |
| 56 | |
| 57 | /* Turn UCC1 & UCC2 on */ |
| 58 | out_8(&bcsr[8], in_8(&bcsr[8]) | BCSR_UCC1_GETH_EN); |
| 59 | out_8(&bcsr[9], in_8(&bcsr[9]) | BCSR_UCC2_GETH_EN); |
| 60 | } |
| 61 | #endif |