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TsiChungLiew8999e6b2008-01-15 13:37:34 -06001/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
TsiChungLiew8999e6b2008-01-15 13:37:34 -06006 */
7
Wolfgang Denk0191e472010-10-26 14:34:52 +02008#include <asm-offsets.h>
TsiChungLiew8999e6b2008-01-15 13:37:34 -06009#include <config.h>
10#include "version.h"
TsiChung Liew0ee47d42010-03-11 22:12:53 -060011#include <asm/cache.h>
TsiChungLiew8999e6b2008-01-15 13:37:34 -060012
13#ifndef CONFIG_IDENT_STRING
14#define CONFIG_IDENT_STRING ""
15#endif
16
TsiChungLiew8999e6b2008-01-15 13:37:34 -060017#define _START _start
18#define _FAULT _fault
19
20#define SAVE_ALL \
21 move.w #0x2700,%sr; /* disable intrs */ \
22 subl #60,%sp; /* space for 15 regs */ \
23 moveml %d0-%d7/%a0-%a6,%sp@;
24
25#define RESTORE_ALL \
26 moveml %sp@,%d0-%d7/%a0-%a6; \
27 addl #60,%sp; /* space for 15 regs */ \
28 rte;
29
30.text
31/*
32 * Vector table. This is used for initial platform startup.
33 * These vectors are to catch any un-intended traps.
34 */
35_vectors:
36
37INITSP: .long 0x00000000 /* Initial SP */
Wolfgang Denka1be4762008-05-20 16:00:29 +020038INITPC: .long _START /* Initial PC */
TsiChungLiew8999e6b2008-01-15 13:37:34 -060039vector02: .long _FAULT /* Access Error */
40vector03: .long _FAULT /* Address Error */
41vector04: .long _FAULT /* Illegal Instruction */
42vector05: .long _FAULT /* Reserved */
43vector06: .long _FAULT /* Reserved */
44vector07: .long _FAULT /* Reserved */
45vector08: .long _FAULT /* Privilege Violation */
46vector09: .long _FAULT /* Trace */
47vector0A: .long _FAULT /* Unimplemented A-Line */
48vector0B: .long _FAULT /* Unimplemented F-Line */
49vector0C: .long _FAULT /* Debug Interrupt */
50vector0D: .long _FAULT /* Reserved */
51vector0E: .long _FAULT /* Format Error */
52vector0F: .long _FAULT /* Unitialized Int. */
53
54/* Reserved */
55vector10_17:
56.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
57
58vector18: .long _FAULT /* Spurious Interrupt */
59vector19: .long _FAULT /* Autovector Level 1 */
60vector1A: .long _FAULT /* Autovector Level 2 */
61vector1B: .long _FAULT /* Autovector Level 3 */
62vector1C: .long _FAULT /* Autovector Level 4 */
63vector1D: .long _FAULT /* Autovector Level 5 */
64vector1E: .long _FAULT /* Autovector Level 6 */
65vector1F: .long _FAULT /* Autovector Level 7 */
66
67/* TRAP #0 - #15 */
68vector20_2F:
69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
70.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
71
72/* Reserved */
73vector30_3F:
74.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
75.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
76
77vector64_127:
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
81.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
82.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
85.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
86
87vector128_191:
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
93.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
94.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
95.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
96
97vector192_255:
98.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
100.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
101.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
102.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
103.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
104.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
105.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
106
107 .text
108
109 .globl _start
110_start:
111 nop
112 nop
113 move.w #0x2700,%sr /* Mask off Interrupt */
114
115 /* Set vector base register at the beginning of the Flash */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116 move.l #CONFIG_SYS_FLASH_BASE, %d0
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600117 movec %d0, %VBR
118
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200119 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600120 movec %d0, %RAMBAR0
121
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200122 move.l #(CONFIG_SYS_INIT_RAM1_ADDR + CONFIG_SYS_INIT_RAM1_CTRL), %d0
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600123 movec %d0, %RAMBAR1
124
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200125 move.l #CONFIG_SYS_MBAR, %d0 /* set MBAR address */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600126 move.c %d0, %MBAR
127
128 /* invalidate and disable cache */
129 move.l #0x01040100, %d0 /* Invalidate cache cmd */
130 movec %d0, %CACR /* Invalidate cache */
131 move.l #0, %d0
132 movec %d0, %ACR0
133 movec %d0, %ACR1
134 movec %d0, %ACR2
135 movec %d0, %ACR3
136
137 /* initialize general use internal ram */
138 move.l #0, %d0
139 move.l #(ICACHE_STATUS), %a1 /* icache */
140 move.l #(DCACHE_STATUS), %a2 /* icache */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600141 move.l %d0, (%a1)
142 move.l %d0, (%a2)
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600143
144 /* set stackpointer to end of internal ram to get some stackspace for the
145 first c-code */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200146 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600147 clr.l %sp@-
148
149 move.l #__got_start, %a5 /* put relocation table address to a5 */
150
Philippe De Muyter2f76a002012-10-03 13:28:42 +0000151 jbsr cpu_init_f /* run low-level CPU init code (from flash) */
152 jbsr board_init_f /* run low-level board init code (from flash) */
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600153
154 /* board_init_f() does not return */
155
156/*------------------------------------------------------------------------------*/
157
158/*
159 * void relocate_code (addr_sp, gd, addr_moni)
160 *
161 * This "function" does not return, instead it continues in RAM
162 * after relocating the monitor code.
163 *
164 * r3 = dest
165 * r4 = src
166 * r5 = length in bytes
167 * r6 = cachelinesize
168 */
169 .globl relocate_code
170relocate_code:
171 link.w %a6,#0
172 move.l 8(%a6), %sp /* set new stack pointer */
173
174 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
175 move.l 16(%a6), %a0 /* Save copy of Destination Address */
176
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200177 move.l #CONFIG_SYS_MONITOR_BASE, %a1
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600178 move.l #__init_end, %a2
179 move.l %a0, %a3
180
181 /* copy the code to RAM */
1821:
183 move.l (%a1)+, (%a3)+
184 cmp.l %a1,%a2
185 bgt.s 1b
186
187/*
188 * We are done. Do not return, instead branch to second part of board
189 * initialization, now running from RAM.
190 */
191 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200192 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600193 jmp (%a1)
194
195in_ram:
196
197clear_bss:
198 /*
199 * Now clear BSS segment
200 */
201 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600203 move.l %a0, %d1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200204 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
TsiChungLiew8999e6b2008-01-15 13:37:34 -06002056:
206 clr.l (%a1)+
207 cmp.l %a1,%d1
208 bgt.s 6b
209
210 /*
211 * fix got table in RAM
212 */
213 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200214 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600215 move.l %a1,%a5 /* * fix got pointer register a5 */
216
217 move.l %a0, %a2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200218 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600219
2207:
221 move.l (%a1),%d1
222 sub.l #_start,%d1
223 add.l %a0,%d1
224 move.l %d1,(%a1)+
225 cmp.l %a2, %a1
226 bne 7b
227
228 /* calculate relative jump to board_init_r in ram */
229 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200230 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600231
232 /* set parameters for board_init_r */
233 move.l %a0,-(%sp) /* dest_addr */
234 move.l %d0,-(%sp) /* gd */
235 jsr (%a1)
236
237/*------------------------------------------------------------------------------*/
238/* exception code */
239 .globl _fault
240_fault:
TsiChung Liew160e11e2008-06-18 19:12:13 -0500241 bra _fault
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600242 .globl _exc_handler
243
244_exc_handler:
245 SAVE_ALL
246 movel %sp,%sp@-
247 bsr exc_handler
248 addql #4,%sp
249 RESTORE_ALL
250
251 .globl _int_handler
252_int_handler:
253 SAVE_ALL
254 movel %sp,%sp@-
255 bsr int_handler
256 addql #4,%sp
257 RESTORE_ALL
258
259/*------------------------------------------------------------------------------*/
TsiChungLiew8999e6b2008-01-15 13:37:34 -0600260
261 .globl version_string
262version_string:
Andreas Bießmann61d01952011-07-18 20:24:04 +0200263 .ascii U_BOOT_VERSION_STRING, "\0"
TsiChung Liew9d636e92008-03-28 08:47:45 -0500264 .align 4