| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| Tom Warren | 13ac544 | 2012-12-11 13:34:12 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. |
| Tom Warren | 13ac544 | 2012-12-11 13:34:12 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _TEGRA30_GP_PADCTRL_H_ |
| 7 | #define _TEGRA30_GP_PADCTRL_H_ |
| 8 | |
| 9 | #include <asm/arch-tegra/gp_padctrl.h> |
| 10 | |
| 11 | /* APB_MISC_GP and padctrl registers */ |
| 12 | struct apb_misc_gp_ctlr { |
| 13 | u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ |
| 14 | u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ |
| 15 | u32 reserved0[22]; /* 0x08 - 0x5C: */ |
| 16 | u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ |
| 17 | u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ |
| 18 | u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ |
| 19 | u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */ |
| 20 | u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ |
| 21 | u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ |
| 22 | u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ |
| 23 | u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ |
| 24 | u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ |
| 25 | u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ |
| 26 | u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ |
| 27 | u32 csuscfg; /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */ |
| 28 | u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ |
| 29 | u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ |
| 30 | u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ |
| 31 | u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ |
| 32 | u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ |
| 33 | u32 lcdcfg1; /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */ |
| 34 | u32 lcdcfg2; /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */ |
| 35 | u32 sdio2cfg; /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */ |
| 36 | u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ |
| 37 | u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ |
| 38 | u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ |
| 39 | u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ |
| 40 | u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ |
| 41 | u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ |
| 42 | u32 vicfg1; /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */ |
| 43 | u32 vivttgen; /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */ |
| 44 | u32 reserved1[7]; /* 0xD0-0xE8: */ |
| 45 | u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ |
| 46 | }; |
| 47 | |
| Tom Warren | 7110b95 | 2013-03-06 16:16:22 -0700 | [diff] [blame] | 48 | /* SDMMC1/3 settings from section 24.6 of T30 TRM */ |
| 49 | #define SDIOCFG_DRVUP_SLWF 1 |
| 50 | #define SDIOCFG_DRVDN_SLWR 1 |
| 51 | #define SDIOCFG_DRVUP 0x2E |
| 52 | #define SDIOCFG_DRVDN 0x2A |
| 53 | |
| Tom Warren | 13ac544 | 2012-12-11 13:34:12 +0000 | [diff] [blame] | 54 | #endif /* _TEGRA30_GP_PADCTRL_H_ */ |