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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mingkai Hu0e58b512015-10-26 19:47:50 +08002/*
3 * Copyright 2015 Freescale Semiconductor, Inc.
Yangbo Lu49dd6e42019-05-23 11:05:45 +08004 * Copyright 2019 NXP Semiconductors
Mingkai Hu0e58b512015-10-26 19:47:50 +08005 *
Mingkai Hu0e58b512015-10-26 19:47:50 +08006 */
7
8#ifndef __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
9#define __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
10
Mingkai Hu0e58b512015-10-26 19:47:50 +080011enum mxc_clock {
12 MXC_ARM_CLK = 0,
13 MXC_BUS_CLK,
14 MXC_UART_CLK,
Mingkai Hu0e58b512015-10-26 19:47:50 +080015 MXC_I2C_CLK,
16 MXC_DSPI_CLK,
17};
18
19unsigned int mxc_get_clock(enum mxc_clock clk);
Simon Glass243182c2017-05-17 08:23:06 -060020ulong get_ddr_freq(ulong);
21uint get_svr(void);
Mingkai Hu0e58b512015-10-26 19:47:50 +080022
23#endif /* __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ */