Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 504384e23f22fcb11641868e58935ba2b1034566 / . / test / dm / dma.c
blob: cce47cb218039649519435c23b8a1a8e6c1232c4 [file] [log] [blame]
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Direct Memory Access U-Class tests
4 *
5 * Copyright (C) 2018 Texas Instruments Incorporated <www.ti.com>
6 * Grygorii Strashko <grygorii.strashko@ti.com>
7 */
8
9#include <common.h>
10#include <dm.h>
Simon Glass9bc15642020-02-03 07:36:16 -0700[diff] [blame]11#include <malloc.h>
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]12#include <dm/test.h>
13#include <dma.h>
Simon Glass75c4d412020-07-19 10:15:37 -0600[diff] [blame]14#include <test/test.h>
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]15#include <test/ut.h>
16
17static int dm_test_dma_m2m(struct unit_test_state *uts)
18{
19 struct udevice *dev;
20 struct dma dma_m2m;
21 u8 src_buf[512];
22 u8 dst_buf[512];
23 size_t len = 512;
24 int i;
25
26 ut_assertok(uclass_get_device_by_name(UCLASS_DMA, "dma", &dev));
27 ut_assertok(dma_get_by_name(dev, "m2m", &dma_m2m));
28
29 memset(dst_buf, 0, len);
30 for (i = 0; i < len; i++)
31 src_buf[i] = i;
32
33 ut_assertok(dma_memcpy(dst_buf, src_buf, len));
Simon Glassa3186e62020-05-10 12:52:45 -0600[diff] [blame]34 ut_asserteq_mem(src_buf, dst_buf, len);
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]35
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]36 return 0;
37}
Simon Glass974dccd2020-07-28 19:41:12 -0600[diff] [blame]38DM_TEST(dm_test_dma_m2m, UT_TESTF_SCAN_FDT);
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]39
40static int dm_test_dma(struct unit_test_state *uts)
41{
42 struct udevice *dev;
43 struct dma dma_tx, dma_rx;
44 u8 src_buf[512];
45 u8 dst_buf[512];
46 void *dst_ptr;
47 size_t len = 512;
48 u32 meta1, meta2;
49 int i;
50
51 ut_assertok(uclass_get_device_by_name(UCLASS_DMA, "dma", &dev));
52
53 ut_assertok(dma_get_by_name(dev, "tx0", &dma_tx));
54 ut_assertok(dma_get_by_name(dev, "rx0", &dma_rx));
55
56 ut_assertok(dma_enable(&dma_tx));
57 ut_assertok(dma_enable(&dma_rx));
58
59 memset(dst_buf, 0, len);
60 for (i = 0; i < len; i++)
61 src_buf[i] = i;
62 meta1 = 0xADADDEAD;
63 meta2 = 0;
64 dst_ptr = &dst_buf;
65
66 ut_assertok(dma_send(&dma_tx, src_buf, len, &meta1));
67
68 ut_asserteq(len, dma_receive(&dma_rx, &dst_ptr, &meta2));
69 ut_asserteq(0xADADDEAD, meta2);
70
71 ut_assertok(dma_disable(&dma_tx));
72 ut_assertok(dma_disable(&dma_rx));
73
74 ut_assertok(dma_free(&dma_tx));
75 ut_assertok(dma_free(&dma_rx));
Simon Glassa3186e62020-05-10 12:52:45 -0600[diff] [blame]76 ut_asserteq_mem(src_buf, dst_buf, len);
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]77
78 return 0;
79}
Simon Glass974dccd2020-07-28 19:41:12 -0600[diff] [blame]80DM_TEST(dm_test_dma, UT_TESTF_SCAN_FDT);
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]81
82static int dm_test_dma_rx(struct unit_test_state *uts)
83{
84 struct udevice *dev;
85 struct dma dma_tx, dma_rx;
86 u8 src_buf[512];
87 u8 dst_buf[512];
88 void *dst_ptr;
89 size_t len = 512;
90 u32 meta1, meta2;
91 int i;
92
93 ut_assertok(uclass_get_device_by_name(UCLASS_DMA, "dma", &dev));
94
95 ut_assertok(dma_get_by_name(dev, "tx0", &dma_tx));
96 ut_assertok(dma_get_by_name(dev, "rx0", &dma_rx));
97
98 ut_assertok(dma_enable(&dma_tx));
99 ut_assertok(dma_enable(&dma_rx));
100
101 memset(dst_buf, 0, len);
102 for (i = 0; i < len; i++)
103 src_buf[i] = i;
104 meta1 = 0xADADDEAD;
105 meta2 = 0;
106 dst_ptr = NULL;
107
108 ut_assertok(dma_prepare_rcv_buf(&dma_tx, dst_buf, len));
109
110 ut_assertok(dma_send(&dma_tx, src_buf, len, &meta1));
111
112 ut_asserteq(len, dma_receive(&dma_rx, &dst_ptr, &meta2));
113 ut_asserteq(0xADADDEAD, meta2);
114 ut_asserteq_ptr(dst_buf, dst_ptr);
115
116 ut_assertok(dma_disable(&dma_tx));
117 ut_assertok(dma_disable(&dma_rx));
118
119 ut_assertok(dma_free(&dma_tx));
120 ut_assertok(dma_free(&dma_rx));
Simon Glassa3186e62020-05-10 12:52:45 -0600[diff] [blame]121 ut_asserteq_mem(src_buf, dst_buf, len);
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +0100[diff] [blame]122
123 return 0;
124}
Simon Glass974dccd2020-07-28 19:41:12 -0600[diff] [blame]125DM_TEST(dm_test_dma_rx, UT_TESTF_SCAN_FDT);