blob: 443bbdae332fac702268b3f417b00639d52e257d [file] [log] [blame]
Peng Fan525c8762019-08-19 07:54:04 +00001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2019 NXP
4 * Peng Fan <peng.fan@nxp.com>
5 */
6
7#include <common.h>
8#include <clk.h>
9#include <clk-uclass.h>
10#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Peng Fan525c8762019-08-19 07:54:04 +000012#include <asm/arch/clock.h>
13#include <asm/arch/imx-regs.h>
14#include <dt-bindings/clock/imx8mm-clock.h>
15
16#include "clk.h"
17
18#define PLL_1416X_RATE(_rate, _m, _p, _s) \
19 { \
20 .rate = (_rate), \
21 .mdiv = (_m), \
22 .pdiv = (_p), \
23 .sdiv = (_s), \
24 }
25
26#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
27 { \
28 .rate = (_rate), \
29 .mdiv = (_m), \
30 .pdiv = (_p), \
31 .sdiv = (_s), \
32 .kdiv = (_k), \
33 }
34
35static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
36 PLL_1416X_RATE(1800000000U, 225, 3, 0),
37 PLL_1416X_RATE(1600000000U, 200, 3, 0),
38 PLL_1416X_RATE(1200000000U, 300, 3, 1),
39 PLL_1416X_RATE(1000000000U, 250, 3, 1),
40 PLL_1416X_RATE(800000000U, 200, 3, 1),
41 PLL_1416X_RATE(750000000U, 250, 2, 2),
42 PLL_1416X_RATE(700000000U, 350, 3, 2),
43 PLL_1416X_RATE(600000000U, 300, 3, 2),
44};
45
46static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
47 PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
48};
49
50static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
51 .type = PLL_1443X,
52 .rate_table = imx8mm_drampll_tbl,
53 .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
54};
55
56static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
57 .type = PLL_1416X,
58 .rate_table = imx8mm_pll1416x_tbl,
59 .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
60};
61
62static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
63 .type = PLL_1416X,
64 .rate_table = imx8mm_pll1416x_tbl,
65 .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
66};
67
68static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
69static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
70static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
71static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
72static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
73static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
74
75static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
76 "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
77
Frieder Schrempf2d82cf82019-10-23 16:36:44 +000078static const char *imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
Peng Fan525c8762019-08-19 07:54:04 +000079 "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
80
81static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
82 "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
83
Peng Fanee5515d2019-10-22 03:29:48 +000084#ifndef CONFIG_SPL_BUILD
85static const char *imx8mm_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
86 "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
87
88static const char *imx8mm_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
89 "clk_ext3", "clk_ext4", "video_pll1_out", };
90
91static const char *imx8mm_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
92 "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
93#endif
94
Peng Fan525c8762019-08-19 07:54:04 +000095static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
96 "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
97
Ye Li0321edb2020-04-19 02:22:09 -070098static const char *imx8mm_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m",
99 "sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", };
100
Peng Fan525c8762019-08-19 07:54:04 +0000101static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
102 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
103
104static const char *imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
105 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
106
107static const char *imx8mm_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
108 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
109
110static const char *imx8mm_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
111 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
112
113static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
114 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
115
116static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
117 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
118
119static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
120 "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
121
122static const char *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
123 "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
124
Peng Fan2dff8792020-06-27 15:49:28 +0800125static const char *imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
126 "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
127
Ye Li0321edb2020-04-19 02:22:09 -0700128static const char *imx8mm_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
129 "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
130
131static const char *imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
132 "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
133
Frieder Schrempf339beba2021-06-07 14:36:43 +0200134static const char *imx8mm_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
135 "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
136
137static const char *imx8mm_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
138 "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
139
140static const char *imx8mm_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
141 "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
142
Peng Fan525c8762019-08-19 07:54:04 +0000143static int imx8mm_clk_probe(struct udevice *dev)
144{
145 void __iomem *base;
146
147 base = (void *)ANATOP_BASE_ADDR;
148
149 clk_dm(IMX8MM_DRAM_PLL_REF_SEL,
150 imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
151 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
152 clk_dm(IMX8MM_ARM_PLL_REF_SEL,
153 imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
154 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
155 clk_dm(IMX8MM_SYS_PLL1_REF_SEL,
156 imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
157 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
158 clk_dm(IMX8MM_SYS_PLL2_REF_SEL,
159 imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
160 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
161 clk_dm(IMX8MM_SYS_PLL3_REF_SEL,
162 imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
163 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
164
165 clk_dm(IMX8MM_DRAM_PLL,
166 imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
167 base + 0x50, &imx8mm_dram_pll));
168 clk_dm(IMX8MM_ARM_PLL,
169 imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
170 base + 0x84, &imx8mm_arm_pll));
171 clk_dm(IMX8MM_SYS_PLL1,
172 imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
173 base + 0x94, &imx8mm_sys_pll));
174 clk_dm(IMX8MM_SYS_PLL2,
175 imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
176 base + 0x104, &imx8mm_sys_pll));
177 clk_dm(IMX8MM_SYS_PLL3,
178 imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
179 base + 0x114, &imx8mm_sys_pll));
180
181 /* PLL bypass out */
182 clk_dm(IMX8MM_DRAM_PLL_BYPASS,
183 imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
184 dram_pll_bypass_sels,
185 ARRAY_SIZE(dram_pll_bypass_sels),
186 CLK_SET_RATE_PARENT));
187 clk_dm(IMX8MM_ARM_PLL_BYPASS,
188 imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
189 arm_pll_bypass_sels,
190 ARRAY_SIZE(arm_pll_bypass_sels),
191 CLK_SET_RATE_PARENT));
192 clk_dm(IMX8MM_SYS_PLL1_BYPASS,
193 imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
194 sys_pll1_bypass_sels,
195 ARRAY_SIZE(sys_pll1_bypass_sels),
196 CLK_SET_RATE_PARENT));
197 clk_dm(IMX8MM_SYS_PLL2_BYPASS,
198 imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
199 sys_pll2_bypass_sels,
200 ARRAY_SIZE(sys_pll2_bypass_sels),
201 CLK_SET_RATE_PARENT));
202 clk_dm(IMX8MM_SYS_PLL3_BYPASS,
203 imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
204 sys_pll3_bypass_sels,
205 ARRAY_SIZE(sys_pll3_bypass_sels),
206 CLK_SET_RATE_PARENT));
207
208 /* PLL out gate */
209 clk_dm(IMX8MM_DRAM_PLL_OUT,
210 imx_clk_gate("dram_pll_out", "dram_pll_bypass",
211 base + 0x50, 13));
212 clk_dm(IMX8MM_ARM_PLL_OUT,
213 imx_clk_gate("arm_pll_out", "arm_pll_bypass",
214 base + 0x84, 11));
215 clk_dm(IMX8MM_SYS_PLL1_OUT,
216 imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
217 base + 0x94, 11));
218 clk_dm(IMX8MM_SYS_PLL2_OUT,
219 imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
220 base + 0x104, 11));
221 clk_dm(IMX8MM_SYS_PLL3_OUT,
222 imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
223 base + 0x114, 11));
224
225 /* SYS PLL fixed output */
226 clk_dm(IMX8MM_SYS_PLL1_40M,
227 imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
228 clk_dm(IMX8MM_SYS_PLL1_80M,
229 imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
230 clk_dm(IMX8MM_SYS_PLL1_100M,
231 imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
232 clk_dm(IMX8MM_SYS_PLL1_133M,
233 imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
234 clk_dm(IMX8MM_SYS_PLL1_160M,
235 imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
236 clk_dm(IMX8MM_SYS_PLL1_200M,
237 imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
238 clk_dm(IMX8MM_SYS_PLL1_266M,
239 imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
240 clk_dm(IMX8MM_SYS_PLL1_400M,
241 imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
242 clk_dm(IMX8MM_SYS_PLL1_800M,
243 imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
244
245 clk_dm(IMX8MM_SYS_PLL2_50M,
246 imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
247 clk_dm(IMX8MM_SYS_PLL2_100M,
248 imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
249 clk_dm(IMX8MM_SYS_PLL2_125M,
250 imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
251 clk_dm(IMX8MM_SYS_PLL2_166M,
252 imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
253 clk_dm(IMX8MM_SYS_PLL2_200M,
254 imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
255 clk_dm(IMX8MM_SYS_PLL2_250M,
256 imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
257 clk_dm(IMX8MM_SYS_PLL2_333M,
258 imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
259 clk_dm(IMX8MM_SYS_PLL2_500M,
260 imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
261 clk_dm(IMX8MM_SYS_PLL2_1000M,
262 imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
263
264 base = dev_read_addr_ptr(dev);
Sean Andersonb58106d2019-12-24 23:57:47 -0500265 if (!base)
Peng Fan525c8762019-08-19 07:54:04 +0000266 return -EINVAL;
267
268 clk_dm(IMX8MM_CLK_A53_SRC,
269 imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
270 imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels)));
271 clk_dm(IMX8MM_CLK_A53_CG,
272 imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
273 clk_dm(IMX8MM_CLK_A53_DIV,
274 imx_clk_divider2("arm_a53_div", "arm_a53_cg",
275 base + 0x8000, 0, 3));
276
277 clk_dm(IMX8MM_CLK_AHB,
278 imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels,
279 base + 0x9000));
280 clk_dm(IMX8MM_CLK_IPG_ROOT,
281 imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
282
283 clk_dm(IMX8MM_CLK_ENET_AXI,
284 imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels,
285 base + 0x8880));
286 clk_dm(IMX8MM_CLK_NAND_USDHC_BUS,
287 imx8m_clk_composite_critical("nand_usdhc_bus",
288 imx8mm_nand_usdhc_sels,
289 base + 0x8900));
Ye Li0321edb2020-04-19 02:22:09 -0700290 clk_dm(IMX8MM_CLK_USB_BUS,
291 imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80));
Peng Fan525c8762019-08-19 07:54:04 +0000292
293 /* IP */
294 clk_dm(IMX8MM_CLK_USDHC1,
295 imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels,
296 base + 0xac00));
297 clk_dm(IMX8MM_CLK_USDHC2,
298 imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels,
299 base + 0xac80));
300 clk_dm(IMX8MM_CLK_I2C1,
301 imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00));
302 clk_dm(IMX8MM_CLK_I2C2,
303 imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80));
304 clk_dm(IMX8MM_CLK_I2C3,
305 imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
306 clk_dm(IMX8MM_CLK_I2C4,
307 imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
308 clk_dm(IMX8MM_CLK_WDOG,
309 imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
310 clk_dm(IMX8MM_CLK_USDHC3,
311 imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels,
312 base + 0xbc80));
Peng Fan2dff8792020-06-27 15:49:28 +0800313 clk_dm(IMX8MM_CLK_QSPI,
314 imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80));
Ye Li0321edb2020-04-19 02:22:09 -0700315 clk_dm(IMX8MM_CLK_USB_CORE_REF,
316 imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100));
317 clk_dm(IMX8MM_CLK_USB_PHY_REF,
318 imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180));
Frieder Schrempf339beba2021-06-07 14:36:43 +0200319 clk_dm(IMX8MM_CLK_ECSPI1,
320 imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280));
321 clk_dm(IMX8MM_CLK_ECSPI2,
322 imx8m_clk_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300));
323 clk_dm(IMX8MM_CLK_ECSPI3,
324 imx8m_clk_composite("ecspi3", imx8mm_ecspi3_sels, base + 0xc180));
Peng Fan525c8762019-08-19 07:54:04 +0000325
Frieder Schrempf339beba2021-06-07 14:36:43 +0200326 clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
327 imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
328 clk_dm(IMX8MM_CLK_ECSPI2_ROOT,
329 imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
330 clk_dm(IMX8MM_CLK_ECSPI3_ROOT,
331 imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
Peng Fan525c8762019-08-19 07:54:04 +0000332 clk_dm(IMX8MM_CLK_I2C1_ROOT,
333 imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
334 clk_dm(IMX8MM_CLK_I2C2_ROOT,
335 imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
336 clk_dm(IMX8MM_CLK_I2C3_ROOT,
337 imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
338 clk_dm(IMX8MM_CLK_I2C4_ROOT,
339 imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
340 clk_dm(IMX8MM_CLK_OCOTP_ROOT,
341 imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
342 clk_dm(IMX8MM_CLK_USDHC1_ROOT,
343 imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
344 clk_dm(IMX8MM_CLK_USDHC2_ROOT,
345 imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
346 clk_dm(IMX8MM_CLK_WDOG1_ROOT,
347 imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
348 clk_dm(IMX8MM_CLK_WDOG2_ROOT,
349 imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
350 clk_dm(IMX8MM_CLK_WDOG3_ROOT,
351 imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
352 clk_dm(IMX8MM_CLK_USDHC3_ROOT,
353 imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
Peng Fan2dff8792020-06-27 15:49:28 +0800354 clk_dm(IMX8MM_CLK_QSPI_ROOT,
355 imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
Ye Li0321edb2020-04-19 02:22:09 -0700356 clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT,
357 imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
Peng Fan525c8762019-08-19 07:54:04 +0000358
Peng Fanee5515d2019-10-22 03:29:48 +0000359 /* clks not needed in SPL stage */
360#ifndef CONFIG_SPL_BUILD
361 clk_dm(IMX8MM_CLK_ENET_REF,
362 imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels,
363 base + 0xa980));
364 clk_dm(IMX8MM_CLK_ENET_TIMER,
365 imx8m_clk_composite("enet_timer", imx8mm_enet_timer_sels,
366 base + 0xaa00));
367 clk_dm(IMX8MM_CLK_ENET_PHY_REF,
368 imx8m_clk_composite("enet_phy", imx8mm_enet_phy_sels,
369 base + 0xaa80));
370 clk_dm(IMX8MM_CLK_ENET1_ROOT,
371 imx_clk_gate4("enet1_root_clk", "enet_axi",
372 base + 0x40a0, 0));
373#endif
374
Peng Fan525c8762019-08-19 07:54:04 +0000375 return 0;
376}
377
378static const struct udevice_id imx8mm_clk_ids[] = {
379 { .compatible = "fsl,imx8mm-ccm" },
380 { },
381};
382
383U_BOOT_DRIVER(imx8mm_clk) = {
384 .name = "clk_imx8mm",
385 .id = UCLASS_CLK,
386 .of_match = imx8mm_clk_ids,
Sean Anderson35c84642022-03-20 16:34:46 -0400387 .ops = &ccf_clk_ops,
Peng Fan525c8762019-08-19 07:54:04 +0000388 .probe = imx8mm_clk_probe,
389 .flags = DM_FLAG_PRE_RELOC,
390};