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Stefan Roese43f32472007-02-20 10:43:34 +01001/*
Stefan Roese88fbf932010-04-15 16:07:28 +02002 * arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
Stefan Roese43f32472007-02-20 10:43:34 +01003 * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
Stefan Roese964754e2008-04-30 10:49:43 +02004 * DDR2 controller (non Denali Core). Those currently are:
5 *
Grant Ericksonb6933412008-05-22 14:44:14 -07006 * 405: 405EX(r)
Stefan Roese964754e2008-04-30 10:49:43 +02007 * 440/460: 440SP/440SPe/460EX/460GT
Stefan Roese43f32472007-02-20 10:43:34 +01008 *
Grant Ericksonb6933412008-05-22 14:44:14 -07009 * Copyright (c) 2008 Nuovation System Designs, LLC
10 * Grant Erickson <gerickson@nuovations.com>
11
Stefan Roesecb9ebd02009-09-28 17:33:45 +020012 * (C) Copyright 2007-2009
Stefan Roese43f32472007-02-20 10:43:34 +010013 * Stefan Roese, DENX Software Engineering, sr@denx.de.
14 *
15 * COPYRIGHT AMCC CORPORATION 2004
16 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +020017 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese43f32472007-02-20 10:43:34 +010018 */
19
20/* define DEBUG for debugging output (obviously ;-)) */
21#if 0
22#define DEBUG
23#endif
24
25#include <common.h>
Stefan Roesebad41112007-03-01 21:11:36 +010026#include <command.h>
Stefan Roese247e9d72010-09-09 19:18:00 +020027#include <asm/ppc4xx.h>
Stefan Roese43f32472007-02-20 10:43:34 +010028#include <i2c.h>
29#include <asm/io.h>
30#include <asm/processor.h>
31#include <asm/mmu.h>
Stefan Roese286b81b2008-04-29 13:57:07 +020032#include <asm/cache.h>
Stefan Roese43f32472007-02-20 10:43:34 +010033
Stefan Roesecb9ebd02009-09-28 17:33:45 +020034#include "ecc.h"
35
Stefan Roese2001a332008-07-10 15:32:32 +020036#define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
37 do { \
38 u32 data; \
39 mfsdram(SDRAM_##mnemonic, data); \
40 printf("%20s[%02x] = 0x%08X\n", \
41 "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
42 } while (0)
43
Felix Radensky8d4d4a62009-07-01 11:37:46 +030044#define PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(mnemonic) \
45 do { \
46 u32 data; \
47 data = mfdcr(SDRAM_##mnemonic); \
48 printf("%20s[%02x] = 0x%08X\n", \
49 "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
50 } while (0)
51
Stefan Roesec3bcfce2010-05-25 15:33:14 +020052#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
53static void update_rdcc(void)
54{
55 u32 val;
56
57 /*
58 * Complete RDSS configuration as mentioned on page 7 of the AMCC
59 * PowerPC440SP/SPe DDR2 application note:
60 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
61 *
62 * Or item #10 "10. Complete RDSS configuration" in chapter
63 * "22.2.9 SDRAM Initialization" of AMCC PPC460EX/EXr/GT users
64 * manual.
65 */
66 mfsdram(SDRAM_RTSR, val);
67 if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
68 mfsdram(SDRAM_RDCC, val);
69 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
70 val += 0x40000000;
71 mtsdram(SDRAM_RDCC, val);
72 }
73 }
74}
75#endif
76
Adam Graham446eb8d2008-10-08 10:13:14 -070077#if defined(CONFIG_440)
78/*
79 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
80 * memory region. Right now the cache should still be disabled in U-Boot
81 * because of the EMAC driver, that need its buffer descriptor to be located
82 * in non cached memory.
83 *
84 * If at some time this restriction doesn't apply anymore, just define
85 * CONFIG_4xx_DCACHE in the board config file and this code should setup
86 * everything correctly.
87 */
88#ifdef CONFIG_4xx_DCACHE
89/* enable caching on SDRAM */
90#define MY_TLB_WORD2_I_ENABLE 0
91#else
92/* disable caching on SDRAM */
93#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
94#endif /* CONFIG_4xx_DCACHE */
Felix Radensky0e925362009-09-27 23:56:12 +020095
96void dcbz_area(u32 start_address, u32 num_bytes);
Adam Graham446eb8d2008-10-08 10:13:14 -070097#endif /* CONFIG_440 */
98
Felix Radensky0e925362009-09-27 23:56:12 +020099#define MAXRANKS 4
100#define MAXBXCF 4
101
102#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
103
Stefan Roesecb9ebd02009-09-28 17:33:45 +0200104#if !defined(CONFIG_NAND_SPL)
Felix Radensky0e925362009-09-27 23:56:12 +0200105/*-----------------------------------------------------------------------------+
106 * sdram_memsize
107 *-----------------------------------------------------------------------------*/
Stefan Roesecb9ebd02009-09-28 17:33:45 +0200108phys_size_t sdram_memsize(void)
Felix Radensky0e925362009-09-27 23:56:12 +0200109{
110 phys_size_t mem_size;
111 unsigned long mcopt2;
112 unsigned long mcstat;
113 unsigned long mb0cf;
114 unsigned long sdsz;
115 unsigned long i;
116
117 mem_size = 0;
118
119 mfsdram(SDRAM_MCOPT2, mcopt2);
120 mfsdram(SDRAM_MCSTAT, mcstat);
121
122 /* DDR controller must be enabled and not in self-refresh. */
123 /* Otherwise memsize is zero. */
124 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
125 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
126 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
127 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
128 for (i = 0; i < MAXBXCF; i++) {
129 mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
130 /* Banks enabled */
131 if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
132#if defined(CONFIG_440)
133 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
134#else
135 sdsz = mb0cf & SDRAM_RXBAS_SDSZ_MASK;
136#endif
137 switch(sdsz) {
138 case SDRAM_RXBAS_SDSZ_8:
139 mem_size+=8;
140 break;
141 case SDRAM_RXBAS_SDSZ_16:
142 mem_size+=16;
143 break;
144 case SDRAM_RXBAS_SDSZ_32:
145 mem_size+=32;
146 break;
147 case SDRAM_RXBAS_SDSZ_64:
148 mem_size+=64;
149 break;
150 case SDRAM_RXBAS_SDSZ_128:
151 mem_size+=128;
152 break;
153 case SDRAM_RXBAS_SDSZ_256:
154 mem_size+=256;
155 break;
156 case SDRAM_RXBAS_SDSZ_512:
157 mem_size+=512;
158 break;
159 case SDRAM_RXBAS_SDSZ_1024:
160 mem_size+=1024;
161 break;
162 case SDRAM_RXBAS_SDSZ_2048:
163 mem_size+=2048;
164 break;
165 case SDRAM_RXBAS_SDSZ_4096:
166 mem_size+=4096;
167 break;
168 default:
169 printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
170 , sdsz);
171 mem_size=0;
172 break;
173 }
174 }
175 }
176 }
177
178 return mem_size << 20;
179}
180
181/*-----------------------------------------------------------------------------+
Stefan Roesecb9ebd02009-09-28 17:33:45 +0200182 * is_ecc_enabled
183 *-----------------------------------------------------------------------------*/
184static unsigned long is_ecc_enabled(void)
185{
186 unsigned long val;
187
188 mfsdram(SDRAM_MCOPT1, val);
189
190 return SDRAM_MCOPT1_MCHK_CHK_DECODE(val);
191}
192
193/*-----------------------------------------------------------------------------+
Felix Radensky0e925362009-09-27 23:56:12 +0200194 * board_add_ram_info
195 *-----------------------------------------------------------------------------*/
196void board_add_ram_info(int use_default)
197{
198 PPC4xx_SYS_INFO board_cfg;
199 u32 val;
200
201 if (is_ecc_enabled())
202 puts(" (ECC");
203 else
204 puts(" (ECC not");
205
206 get_sys_info(&board_cfg);
207
Stefan Roesecb9ebd02009-09-28 17:33:45 +0200208#if defined(CONFIG_405EX)
209 val = board_cfg.freqPLB;
210#else
Felix Radensky0e925362009-09-27 23:56:12 +0200211 mfsdr(SDR0_DDR0, val);
212 val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
Felix Radensky0e925362009-09-27 23:56:12 +0200213#endif
214 printf(" enabled, %d MHz", (val * 2) / 1000000);
215
216 mfsdram(SDRAM_MMODE, val);
217 val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
218 printf(", CL%d)", val);
219}
Stefan Roesecb9ebd02009-09-28 17:33:45 +0200220#endif /* !CONFIG_NAND_SPL */
Felix Radensky0e925362009-09-27 23:56:12 +0200221
Stefan Roese2001a332008-07-10 15:32:32 +0200222#if defined(CONFIG_SPD_EEPROM)
Stefan Roese43f32472007-02-20 10:43:34 +0100223
Stefan Roesebad41112007-03-01 21:11:36 +0100224/*-----------------------------------------------------------------------------+
225 * Defines
226 *-----------------------------------------------------------------------------*/
Stefan Roese43f32472007-02-20 10:43:34 +0100227#define SDRAM_DDR1 1
228#define SDRAM_DDR2 2
229#define SDRAM_NONE 0
230
Wolfgang Denk70df7bc2007-06-22 23:59:00 +0200231#define MAXDIMMS 2
Stefan Roese43f32472007-02-20 10:43:34 +0100232#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
233
234#define ONE_BILLION 1000000000
235
Stefan Roesebad41112007-03-01 21:11:36 +0100236#define CMD_NOP (7 << 19)
237#define CMD_PRECHARGE (2 << 19)
238#define CMD_REFRESH (1 << 19)
239#define CMD_EMR (0 << 19)
240#define CMD_READ (5 << 19)
241#define CMD_WRITE (4 << 19)
Stefan Roese43f32472007-02-20 10:43:34 +0100242
Stefan Roesebad41112007-03-01 21:11:36 +0100243#define SELECT_MR (0 << 16)
244#define SELECT_EMR (1 << 16)
245#define SELECT_EMR2 (2 << 16)
246#define SELECT_EMR3 (3 << 16)
247
248/* MR */
249#define DLL_RESET 0x00000100
250
251#define WRITE_RECOV_2 (1 << 9)
252#define WRITE_RECOV_3 (2 << 9)
253#define WRITE_RECOV_4 (3 << 9)
254#define WRITE_RECOV_5 (4 << 9)
255#define WRITE_RECOV_6 (5 << 9)
256
257#define BURST_LEN_4 0x00000002
258
259/* EMR */
260#define ODT_0_OHM 0x00000000
261#define ODT_50_OHM 0x00000044
262#define ODT_75_OHM 0x00000004
263#define ODT_150_OHM 0x00000040
264
265#define ODS_FULL 0x00000000
266#define ODS_REDUCED 0x00000002
Prodyut Hazarika52b6bec2008-08-27 16:39:00 -0700267#define OCD_CALIB_DEF 0x00000380
Stefan Roesebad41112007-03-01 21:11:36 +0100268
269/* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
270#define ODT_EB0R (0x80000000 >> 8)
271#define ODT_EB0W (0x80000000 >> 7)
272#define CALC_ODT_R(n) (ODT_EB0R << (n << 1))
273#define CALC_ODT_W(n) (ODT_EB0W << (n << 1))
274#define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
275
Stefan Roese43f32472007-02-20 10:43:34 +0100276/* Defines for the Read Cycle Delay test */
Stefan Roesef88e3602007-03-31 08:46:08 +0200277#define NUMMEMTESTS 8
278#define NUMMEMWORDS 8
Stefan Roesebd2adeb2007-07-16 09:57:00 +0200279#define NUMLOOPS 64 /* memory test loops */
Stefan Roese43f32472007-02-20 10:43:34 +0100280
Stefan Roesebad41112007-03-01 21:11:36 +0100281/*
Stefan Roese0203a972008-07-09 17:33:57 +0200282 * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
283 * To support such configurations, we "only" map the first 2GB via the TLB's. We
284 * need some free virtual address space for the remaining peripherals like, SoC
285 * devices, FLASH etc.
286 *
287 * Note that ECC is currently not supported on configurations with more than 2GB
288 * SDRAM. This is because we only map the first 2GB on such systems, and therefore
289 * the ECC parity byte of the remaining area can't be written.
290 */
Stefan Roese0203a972008-07-09 17:33:57 +0200291
292/*
Heiko Schocher68310b02007-06-25 19:11:37 +0200293 * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
294 */
295void __spd_ddr_init_hang (void)
296{
297 hang ();
298}
299void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
300
Stefan Roesebd2adeb2007-07-16 09:57:00 +0200301/*
302 * To provide an interface for board specific config values in this common
303 * DDR setup code, we implement he "weak" default functions here. They return
304 * the default value back to the caller.
305 *
306 * Please see include/configs/yucca.h for an example fora board specific
307 * implementation.
308 */
309u32 __ddr_wrdtr(u32 default_val)
310{
311 return default_val;
312}
313u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
314
315u32 __ddr_clktr(u32 default_val)
316{
317 return default_val;
318}
319u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
320
Heiko Schocher633e03a2007-06-22 19:11:54 +0200321
Stefan Roese43f32472007-02-20 10:43:34 +0100322/* Private Structure Definitions */
323
324/* enum only to ease code for cas latency setting */
325typedef enum ddr_cas_id {
326 DDR_CAS_2 = 20,
327 DDR_CAS_2_5 = 25,
328 DDR_CAS_3 = 30,
329 DDR_CAS_4 = 40,
330 DDR_CAS_5 = 50
331} ddr_cas_id_t;
332
333/*-----------------------------------------------------------------------------+
334 * Prototypes
335 *-----------------------------------------------------------------------------*/
Stefan Roese43f32472007-02-20 10:43:34 +0100336static void get_spd_info(unsigned long *dimm_populated,
337 unsigned char *iic0_dimm_addr,
338 unsigned long num_dimm_banks);
339static void check_mem_type(unsigned long *dimm_populated,
340 unsigned char *iic0_dimm_addr,
341 unsigned long num_dimm_banks);
342static void check_frequency(unsigned long *dimm_populated,
343 unsigned char *iic0_dimm_addr,
344 unsigned long num_dimm_banks);
345static void check_rank_number(unsigned long *dimm_populated,
346 unsigned char *iic0_dimm_addr,
347 unsigned long num_dimm_banks);
348static void check_voltage_type(unsigned long *dimm_populated,
349 unsigned char *iic0_dimm_addr,
350 unsigned long num_dimm_banks);
351static void program_memory_queue(unsigned long *dimm_populated,
352 unsigned char *iic0_dimm_addr,
353 unsigned long num_dimm_banks);
354static void program_codt(unsigned long *dimm_populated,
355 unsigned char *iic0_dimm_addr,
356 unsigned long num_dimm_banks);
357static void program_mode(unsigned long *dimm_populated,
358 unsigned char *iic0_dimm_addr,
359 unsigned long num_dimm_banks,
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100360 ddr_cas_id_t *selected_cas,
361 int *write_recovery);
Stefan Roese43f32472007-02-20 10:43:34 +0100362static void program_tr(unsigned long *dimm_populated,
363 unsigned char *iic0_dimm_addr,
364 unsigned long num_dimm_banks);
365static void program_rtr(unsigned long *dimm_populated,
366 unsigned char *iic0_dimm_addr,
367 unsigned long num_dimm_banks);
368static void program_bxcf(unsigned long *dimm_populated,
369 unsigned char *iic0_dimm_addr,
370 unsigned long num_dimm_banks);
371static void program_copt1(unsigned long *dimm_populated,
372 unsigned char *iic0_dimm_addr,
373 unsigned long num_dimm_banks);
374static void program_initplr(unsigned long *dimm_populated,
375 unsigned char *iic0_dimm_addr,
376 unsigned long num_dimm_banks,
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100377 ddr_cas_id_t selected_cas,
Stefan Roesebad41112007-03-01 21:11:36 +0100378 int write_recovery);
Stefan Roeseb39ef632007-03-08 10:06:09 +0100379#ifdef CONFIG_DDR_ECC
Stefan Roese43f32472007-02-20 10:43:34 +0100380static void program_ecc(unsigned long *dimm_populated,
381 unsigned char *iic0_dimm_addr,
Stefan Roesebad41112007-03-01 21:11:36 +0100382 unsigned long num_dimm_banks,
383 unsigned long tlb_word2_i_value);
Stefan Roeseb39ef632007-03-08 10:06:09 +0100384#endif
Adam Graham97a55812008-09-03 12:26:59 -0700385#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
Stefan Roesebad41112007-03-01 21:11:36 +0100386static void program_DQS_calibration(unsigned long *dimm_populated,
Adam Graham97a55812008-09-03 12:26:59 -0700387 unsigned char *iic0_dimm_addr,
388 unsigned long num_dimm_banks);
Stefan Roese43f32472007-02-20 10:43:34 +0100389#ifdef HARD_CODED_DQS /* calibration test with hardvalues */
Wolfgang Denk52232fd2007-02-27 14:26:04 +0100390static void test(void);
Stefan Roese43f32472007-02-20 10:43:34 +0100391#else
Wolfgang Denk52232fd2007-02-27 14:26:04 +0100392static void DQS_calibration_process(void);
Stefan Roese43f32472007-02-20 10:43:34 +0100393#endif
Adam Graham97a55812008-09-03 12:26:59 -0700394#endif
Stefan Roese43f32472007-02-20 10:43:34 +0100395
Stefan Roese43f32472007-02-20 10:43:34 +0100396static unsigned char spd_read(uchar chip, uint addr)
397{
398 unsigned char data[2];
399
400 if (i2c_probe(chip) == 0)
401 if (i2c_read(chip, addr, 1, data, 1) == 0)
402 return data[0];
403
404 return 0;
405}
406
407/*-----------------------------------------------------------------------------+
Stefan Roese43f32472007-02-20 10:43:34 +0100408 * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
409 * Note: This routine runs from flash with a stack set up in the chip's
410 * sram space. It is important that the routine does not require .sbss, .bss or
411 * .data sections. It also cannot call routines that require these sections.
412 *-----------------------------------------------------------------------------*/
413/*-----------------------------------------------------------------------------
Wolfgang Denk52232fd2007-02-27 14:26:04 +0100414 * Function: initdram
Stefan Roese43f32472007-02-20 10:43:34 +0100415 * Description: Configures SDRAM memory banks for DDR operation.
Wolfgang Denk52232fd2007-02-27 14:26:04 +0100416 * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
417 * via the IIC bus and then configures the DDR SDRAM memory
418 * banks appropriately. If Auto Memory Configuration is
419 * not used, it is assumed that no DIMM is plugged
Stefan Roese43f32472007-02-20 10:43:34 +0100420 *-----------------------------------------------------------------------------*/
Becky Brucebd99ae72008-06-09 16:03:40 -0500421phys_size_t initdram(int board_type)
Stefan Roese43f32472007-02-20 10:43:34 +0100422{
Stefan Roesebad41112007-03-01 21:11:36 +0100423 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
Felix Radensky389672f2010-01-19 21:19:06 +0200424 unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
Stefan Roese4a0f5902008-01-15 10:11:02 +0100425 unsigned long num_dimm_banks; /* on board dimm banks */
Stefan Roese43f32472007-02-20 10:43:34 +0100426 unsigned long val;
Stefan Roese4a0f5902008-01-15 10:11:02 +0100427 ddr_cas_id_t selected_cas = DDR_CAS_5; /* preset to silence compiler */
Stefan Roesebad41112007-03-01 21:11:36 +0100428 int write_recovery;
Stefan Roese0203a972008-07-09 17:33:57 +0200429 phys_size_t dram_size = 0;
Stefan Roese43f32472007-02-20 10:43:34 +0100430
431 num_dimm_banks = sizeof(iic0_dimm_addr);
432
433 /*------------------------------------------------------------------
Stefan Roese43f32472007-02-20 10:43:34 +0100434 * Reset the DDR-SDRAM controller.
435 *-----------------------------------------------------------------*/
Stefan Roese95ca5fa2010-09-11 09:31:43 +0200436 mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
Stefan Roese43f32472007-02-20 10:43:34 +0100437 mtsdr(SDR0_SRST, 0x00000000);
438
439 /*
440 * Make sure I2C controller is initialized
441 * before continuing.
442 */
443
444 /* switch to correct I2C bus */
Dirk Eibach42b204f2013-04-25 02:40:01 +0000445 i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
Stefan Roese43f32472007-02-20 10:43:34 +0100446
447 /*------------------------------------------------------------------
448 * Clear out the serial presence detect buffers.
449 * Perform IIC reads from the dimm. Fill in the spds.
450 * Check to see if the dimm slots are populated
451 *-----------------------------------------------------------------*/
452 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
453
454 /*------------------------------------------------------------------
455 * Check the memory type for the dimms plugged.
456 *-----------------------------------------------------------------*/
457 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
458
459 /*------------------------------------------------------------------
460 * Check the frequency supported for the dimms plugged.
461 *-----------------------------------------------------------------*/
462 check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
463
464 /*------------------------------------------------------------------
465 * Check the total rank number.
466 *-----------------------------------------------------------------*/
467 check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
468
469 /*------------------------------------------------------------------
470 * Check the voltage type for the dimms plugged.
471 *-----------------------------------------------------------------*/
472 check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
473
474 /*------------------------------------------------------------------
475 * Program SDRAM controller options 2 register
476 * Except Enabling of the memory controller.
477 *-----------------------------------------------------------------*/
478 mfsdram(SDRAM_MCOPT2, val);
479 mtsdram(SDRAM_MCOPT2,
480 (val &
481 ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
482 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
483 SDRAM_MCOPT2_ISIE_MASK))
484 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
485 SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
486 SDRAM_MCOPT2_ISIE_ENABLE));
487
488 /*------------------------------------------------------------------
489 * Program SDRAM controller options 1 register
490 * Note: Does not enable the memory controller.
491 *-----------------------------------------------------------------*/
492 program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
493
494 /*------------------------------------------------------------------
495 * Set the SDRAM Controller On Die Termination Register
496 *-----------------------------------------------------------------*/
497 program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
498
499 /*------------------------------------------------------------------
500 * Program SDRAM refresh register.
501 *-----------------------------------------------------------------*/
502 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
503
504 /*------------------------------------------------------------------
505 * Program SDRAM mode register.
506 *-----------------------------------------------------------------*/
Stefan Roesebad41112007-03-01 21:11:36 +0100507 program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
508 &selected_cas, &write_recovery);
Stefan Roese43f32472007-02-20 10:43:34 +0100509
510 /*------------------------------------------------------------------
511 * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
512 *-----------------------------------------------------------------*/
513 mfsdram(SDRAM_WRDTR, val);
514 mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
Stefan Roesebd2adeb2007-07-16 09:57:00 +0200515 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
Stefan Roese43f32472007-02-20 10:43:34 +0100516
517 /*------------------------------------------------------------------
518 * Set the SDRAM Clock Timing Register
519 *-----------------------------------------------------------------*/
520 mfsdram(SDRAM_CLKTR, val);
Stefan Roesebd2adeb2007-07-16 09:57:00 +0200521 mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
522 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
Stefan Roese43f32472007-02-20 10:43:34 +0100523
524 /*------------------------------------------------------------------
525 * Program the BxCF registers.
526 *-----------------------------------------------------------------*/
527 program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
528
529 /*------------------------------------------------------------------
530 * Program SDRAM timing registers.
531 *-----------------------------------------------------------------*/
532 program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
533
534 /*------------------------------------------------------------------
535 * Set the Extended Mode register
536 *-----------------------------------------------------------------*/
537 mfsdram(SDRAM_MEMODE, val);
538 mtsdram(SDRAM_MEMODE,
539 (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
540 SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
541 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
Stefan Roeseb39ef632007-03-08 10:06:09 +0100542 | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
Stefan Roese43f32472007-02-20 10:43:34 +0100543
544 /*------------------------------------------------------------------
545 * Program Initialization preload registers.
546 *-----------------------------------------------------------------*/
547 program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
Stefan Roesebad41112007-03-01 21:11:36 +0100548 selected_cas, write_recovery);
Stefan Roese43f32472007-02-20 10:43:34 +0100549
550 /*------------------------------------------------------------------
551 * Delay to ensure 200usec have elapsed since reset.
552 *-----------------------------------------------------------------*/
553 udelay(400);
554
555 /*------------------------------------------------------------------
556 * Set the memory queue core base addr.
557 *-----------------------------------------------------------------*/
558 program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
559
560 /*------------------------------------------------------------------
561 * Program SDRAM controller options 2 register
562 * Enable the memory controller.
563 *-----------------------------------------------------------------*/
564 mfsdram(SDRAM_MCOPT2, val);
565 mtsdram(SDRAM_MCOPT2,
566 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
567 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
Prodyut Hazarika52b6bec2008-08-27 16:39:00 -0700568 SDRAM_MCOPT2_IPTR_EXECUTE);
Stefan Roese43f32472007-02-20 10:43:34 +0100569
570 /*------------------------------------------------------------------
Prodyut Hazarika52b6bec2008-08-27 16:39:00 -0700571 * Wait for IPTR_EXECUTE init sequence to complete.
Stefan Roese43f32472007-02-20 10:43:34 +0100572 *-----------------------------------------------------------------*/
573 do {
574 mfsdram(SDRAM_MCSTAT, val);
575 } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
576
Prodyut Hazarika52b6bec2008-08-27 16:39:00 -0700577 /* enable the controller only after init sequence completes */
578 mfsdram(SDRAM_MCOPT2, val);
579 mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
580
581 /* Make sure delay-line calibration is done before proceeding */
582 do {
583 mfsdram(SDRAM_DLCR, val);
584 } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
585
Stefan Roese43f32472007-02-20 10:43:34 +0100586 /* get installed memory size */
587 dram_size = sdram_memsize();
588
Stefan Roese0203a972008-07-09 17:33:57 +0200589 /*
590 * Limit size to 2GB
591 */
592 if (dram_size > CONFIG_MAX_MEM_MAPPED)
593 dram_size = CONFIG_MAX_MEM_MAPPED;
594
Stefan Roese43f32472007-02-20 10:43:34 +0100595 /* and program tlb entries for this size (dynamic) */
Stefan Roesebd2adeb2007-07-16 09:57:00 +0200596
597 /*
598 * Program TLB entries with caches enabled, for best performace
599 * while auto-calibrating and ECC generation
600 */
601 program_tlb(0, 0, dram_size, 0);
Stefan Roese43f32472007-02-20 10:43:34 +0100602
Stefan Roese43f32472007-02-20 10:43:34 +0100603 /*------------------------------------------------------------------
Stefan Roesebad41112007-03-01 21:11:36 +0100604 * DQS calibration.
Stefan Roese43f32472007-02-20 10:43:34 +0100605 *-----------------------------------------------------------------*/
Adam Graham97a55812008-09-03 12:26:59 -0700606#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
607 DQS_autocalibration();
608#else
Stefan Roesebad41112007-03-01 21:11:36 +0100609 program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
Adam Graham97a55812008-09-03 12:26:59 -0700610#endif
Stefan Roesec3bcfce2010-05-25 15:33:14 +0200611 /*
612 * Now complete RDSS configuration as mentioned on page 7 of the AMCC
613 * PowerPC440SP/SPe DDR2 application note:
614 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
615 */
616 update_rdcc();
Stefan Roese43f32472007-02-20 10:43:34 +0100617
Stefan Roeseb39ef632007-03-08 10:06:09 +0100618#ifdef CONFIG_DDR_ECC
Stefan Roese43f32472007-02-20 10:43:34 +0100619 /*------------------------------------------------------------------
Stefan Roesebad41112007-03-01 21:11:36 +0100620 * If ecc is enabled, initialize the parity bits.
Stefan Roese43f32472007-02-20 10:43:34 +0100621 *-----------------------------------------------------------------*/
Stefan Roesebd2adeb2007-07-16 09:57:00 +0200622 program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
Stefan Roeseb39ef632007-03-08 10:06:09 +0100623#endif
Stefan Roese43f32472007-02-20 10:43:34 +0100624
Stefan Roesebd2adeb2007-07-16 09:57:00 +0200625 /*
Stefan Roesefae16c92011-09-16 12:54:58 +0200626 * Flush the dcache before removing the TLB with caches
627 * enabled. Otherwise this might lead to problems later on,
628 * e.g. while booting Linux (as seen on ICON-440SPe).
629 */
630 flush_dcache();
631
632 /*
Stefan Roesebd2adeb2007-07-16 09:57:00 +0200633 * Now after initialization (auto-calibration and ECC generation)
634 * remove the TLB entries with caches enabled and program again with
635 * desired cache functionality
636 */
637 remove_tlb(0, dram_size);
638 program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
639
Grant Erickson9416cd92008-07-09 16:46:35 -0700640 ppc4xx_ibm_ddr2_register_dump();
Stefan Roese43f32472007-02-20 10:43:34 +0100641
Stefan Roesebdd13d12008-03-11 15:05:26 +0100642 /*
643 * Clear potential errors resulting from auto-calibration.
644 * If not done, then we could get an interrupt later on when
645 * exceptions are enabled.
646 */
647 set_mcsr(get_mcsr());
648
Stefan Roese0203a972008-07-09 17:33:57 +0200649 return sdram_memsize();
Stefan Roese43f32472007-02-20 10:43:34 +0100650}
651
652static void get_spd_info(unsigned long *dimm_populated,
653 unsigned char *iic0_dimm_addr,
654 unsigned long num_dimm_banks)
655{
656 unsigned long dimm_num;
657 unsigned long dimm_found;
658 unsigned char num_of_bytes;
659 unsigned char total_size;
660
York Sun4a598092013-04-01 11:29:11 -0700661 dimm_found = false;
Stefan Roese43f32472007-02-20 10:43:34 +0100662 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
663 num_of_bytes = 0;
664 total_size = 0;
665
666 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
667 debug("\nspd_read(0x%x) returned %d\n",
668 iic0_dimm_addr[dimm_num], num_of_bytes);
669 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
670 debug("spd_read(0x%x) returned %d\n",
671 iic0_dimm_addr[dimm_num], total_size);
672
673 if ((num_of_bytes != 0) && (total_size != 0)) {
York Sun4a598092013-04-01 11:29:11 -0700674 dimm_populated[dimm_num] = true;
675 dimm_found = true;
Stefan Roese43f32472007-02-20 10:43:34 +0100676 debug("DIMM slot %lu: populated\n", dimm_num);
677 } else {
York Sun4a598092013-04-01 11:29:11 -0700678 dimm_populated[dimm_num] = false;
Stefan Roese43f32472007-02-20 10:43:34 +0100679 debug("DIMM slot %lu: Not populated\n", dimm_num);
680 }
681 }
682
York Sun4a598092013-04-01 11:29:11 -0700683 if (dimm_found == false) {
Stefan Roese43f32472007-02-20 10:43:34 +0100684 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
Heiko Schocher68310b02007-06-25 19:11:37 +0200685 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +0100686 }
687}
688
Stefan Roese43f32472007-02-20 10:43:34 +0100689
690/*------------------------------------------------------------------
691 * For the memory DIMMs installed, this routine verifies that they
692 * really are DDR specific DIMMs.
693 *-----------------------------------------------------------------*/
694static void check_mem_type(unsigned long *dimm_populated,
695 unsigned char *iic0_dimm_addr,
696 unsigned long num_dimm_banks)
697{
698 unsigned long dimm_num;
699 unsigned long dimm_type;
700
701 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
York Sun4a598092013-04-01 11:29:11 -0700702 if (dimm_populated[dimm_num] == true) {
Stefan Roese43f32472007-02-20 10:43:34 +0100703 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
704 switch (dimm_type) {
705 case 1:
706 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
707 "slot %d.\n", (unsigned int)dimm_num);
708 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
709 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schocher68310b02007-06-25 19:11:37 +0200710 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +0100711 break;
712 case 2:
713 printf("ERROR: EDO DIMM detected in slot %d.\n",
714 (unsigned int)dimm_num);
715 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
716 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schocher68310b02007-06-25 19:11:37 +0200717 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +0100718 break;
719 case 3:
720 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
721 (unsigned int)dimm_num);
722 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
723 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schocher68310b02007-06-25 19:11:37 +0200724 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +0100725 break;
726 case 4:
727 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
728 (unsigned int)dimm_num);
729 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
730 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schocher68310b02007-06-25 19:11:37 +0200731 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +0100732 break;
733 case 5:
734 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
735 (unsigned int)dimm_num);
736 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
737 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schocher68310b02007-06-25 19:11:37 +0200738 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +0100739 break;
740 case 6:
741 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
742 (unsigned int)dimm_num);
743 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
744 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schocher68310b02007-06-25 19:11:37 +0200745 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +0100746 break;
747 case 7:
Felix Radensky8d4d4a62009-07-01 11:37:46 +0300748 debug("DIMM slot %lu: DDR1 SDRAM detected\n", dimm_num);
Stefan Roese43f32472007-02-20 10:43:34 +0100749 dimm_populated[dimm_num] = SDRAM_DDR1;
750 break;
751 case 8:
Felix Radensky8d4d4a62009-07-01 11:37:46 +0300752 debug("DIMM slot %lu: DDR2 SDRAM detected\n", dimm_num);
Stefan Roese43f32472007-02-20 10:43:34 +0100753 dimm_populated[dimm_num] = SDRAM_DDR2;
754 break;
755 default:
756 printf("ERROR: Unknown DIMM detected in slot %d.\n",
757 (unsigned int)dimm_num);
758 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
759 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schocher68310b02007-06-25 19:11:37 +0200760 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +0100761 break;
762 }
763 }
764 }
765 for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
766 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
767 && (dimm_populated[dimm_num] != SDRAM_NONE)
768 && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
769 printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
Heiko Schocher68310b02007-06-25 19:11:37 +0200770 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +0100771 }
772 }
773}
774
775/*------------------------------------------------------------------
776 * For the memory DIMMs installed, this routine verifies that
777 * frequency previously calculated is supported.
778 *-----------------------------------------------------------------*/
779static void check_frequency(unsigned long *dimm_populated,
780 unsigned char *iic0_dimm_addr,
781 unsigned long num_dimm_banks)
782{
783 unsigned long dimm_num;
784 unsigned long tcyc_reg;
785 unsigned long cycle_time;
786 unsigned long calc_cycle_time;
787 unsigned long sdram_freq;
788 unsigned long sdr_ddrpll;
Stefan Roeseedd73f22007-10-21 08:12:41 +0200789 PPC4xx_SYS_INFO board_cfg;
Stefan Roese43f32472007-02-20 10:43:34 +0100790
791 /*------------------------------------------------------------------
792 * Get the board configuration info.
793 *-----------------------------------------------------------------*/
794 get_sys_info(&board_cfg);
795
Stefan Roeseb39ef632007-03-08 10:06:09 +0100796 mfsdr(SDR0_DDR0, sdr_ddrpll);
Stefan Roese43f32472007-02-20 10:43:34 +0100797 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
798
799 /*
800 * calc_cycle_time is calculated from DDR frequency set by board/chip
801 * and is expressed in multiple of 10 picoseconds
802 * to match the way DIMM cycle time is calculated below.
803 */
804 calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
805
806 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
807 if (dimm_populated[dimm_num] != SDRAM_NONE) {
808 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
809 /*
810 * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
811 * the higher order nibble (bits 4-7) designates the cycle time
812 * to a granularity of 1ns;
813 * the value presented by the lower order nibble (bits 0-3)
814 * has a granularity of .1ns and is added to the value designated
815 * by the higher nibble. In addition, four lines of the lower order
816 * nibble are assigned to support +.25,+.33, +.66 and +.75.
817 */
818 /* Convert from hex to decimal */
819 if ((tcyc_reg & 0x0F) == 0x0D)
820 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
821 else if ((tcyc_reg & 0x0F) == 0x0C)
822 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
823 else if ((tcyc_reg & 0x0F) == 0x0B)
824 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
825 else if ((tcyc_reg & 0x0F) == 0x0A)
826 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
827 else
828 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
829 ((tcyc_reg & 0x0F)*10);
Felix Radensky8d4d4a62009-07-01 11:37:46 +0300830 debug("cycle_time=%lu [10 picoseconds]\n", cycle_time);
Stefan Roese43f32472007-02-20 10:43:34 +0100831
832 if (cycle_time > (calc_cycle_time + 10)) {
833 /*
834 * the provided sdram cycle_time is too small
835 * for the available DIMM cycle_time.
836 * The additionnal 100ps is here to accept a small incertainty.
837 */
838 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
839 "slot %d \n while calculated cycle time is %d ps.\n",
840 (unsigned int)(cycle_time*10),
841 (unsigned int)dimm_num,
842 (unsigned int)(calc_cycle_time*10));
843 printf("Replace the DIMM, or change DDR frequency via "
844 "strapping bits.\n\n");
Heiko Schocher68310b02007-06-25 19:11:37 +0200845 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +0100846 }
847 }
848 }
849}
850
851/*------------------------------------------------------------------
852 * For the memory DIMMs installed, this routine verifies two
853 * ranks/banks maximum are availables.
854 *-----------------------------------------------------------------*/
855static void check_rank_number(unsigned long *dimm_populated,
856 unsigned char *iic0_dimm_addr,
857 unsigned long num_dimm_banks)
858{
859 unsigned long dimm_num;
860 unsigned long dimm_rank;
861 unsigned long total_rank = 0;
862
863 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
864 if (dimm_populated[dimm_num] != SDRAM_NONE) {
865 dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
866 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
867 dimm_rank = (dimm_rank & 0x0F) +1;
868 else
869 dimm_rank = dimm_rank & 0x0F;
870
871
872 if (dimm_rank > MAXRANKS) {
Stefan Roese251161b2008-07-10 09:58:06 +0200873 printf("ERROR: DRAM DIMM detected with %lu ranks in "
874 "slot %lu is not supported.\n", dimm_rank, dimm_num);
Stefan Roese43f32472007-02-20 10:43:34 +0100875 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
876 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schocher68310b02007-06-25 19:11:37 +0200877 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +0100878 } else
879 total_rank += dimm_rank;
880 }
881 if (total_rank > MAXRANKS) {
882 printf("ERROR: DRAM DIMM detected with a total of %d ranks "
883 "for all slots.\n", (unsigned int)total_rank);
884 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
885 printf("Remove one of the DIMM modules.\n\n");
Heiko Schocher68310b02007-06-25 19:11:37 +0200886 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +0100887 }
888 }
889}
890
891/*------------------------------------------------------------------
892 * only support 2.5V modules.
893 * This routine verifies this.
894 *-----------------------------------------------------------------*/
895static void check_voltage_type(unsigned long *dimm_populated,
896 unsigned char *iic0_dimm_addr,
897 unsigned long num_dimm_banks)
898{
899 unsigned long dimm_num;
900 unsigned long voltage_type;
901
902 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
903 if (dimm_populated[dimm_num] != SDRAM_NONE) {
904 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
905 switch (voltage_type) {
906 case 0x00:
907 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
908 printf("This DIMM is 5.0 Volt/TTL.\n");
909 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
910 (unsigned int)dimm_num);
Heiko Schocher68310b02007-06-25 19:11:37 +0200911 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +0100912 break;
913 case 0x01:
914 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
915 printf("This DIMM is LVTTL.\n");
916 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
917 (unsigned int)dimm_num);
Heiko Schocher68310b02007-06-25 19:11:37 +0200918 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +0100919 break;
920 case 0x02:
921 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
922 printf("This DIMM is 1.5 Volt.\n");
923 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
924 (unsigned int)dimm_num);
Heiko Schocher68310b02007-06-25 19:11:37 +0200925 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +0100926 break;
927 case 0x03:
928 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
929 printf("This DIMM is 3.3 Volt/TTL.\n");
930 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
931 (unsigned int)dimm_num);
Heiko Schocher68310b02007-06-25 19:11:37 +0200932 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +0100933 break;
934 case 0x04:
935 /* 2.5 Voltage only for DDR1 */
936 break;
937 case 0x05:
938 /* 1.8 Voltage only for DDR2 */
939 break;
940 default:
941 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
942 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
943 (unsigned int)dimm_num);
Heiko Schocher68310b02007-06-25 19:11:37 +0200944 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +0100945 break;
946 }
947 }
948 }
949}
950
951/*-----------------------------------------------------------------------------+
952 * program_copt1.
953 *-----------------------------------------------------------------------------*/
954static void program_copt1(unsigned long *dimm_populated,
955 unsigned char *iic0_dimm_addr,
956 unsigned long num_dimm_banks)
957{
958 unsigned long dimm_num;
959 unsigned long mcopt1;
960 unsigned long ecc_enabled;
961 unsigned long ecc = 0;
962 unsigned long data_width = 0;
963 unsigned long dimm_32bit;
964 unsigned long dimm_64bit;
965 unsigned long registered = 0;
966 unsigned long attribute = 0;
967 unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
968 unsigned long bankcount;
Stefan Roese43f32472007-02-20 10:43:34 +0100969 unsigned long val;
970
Stefan Roeseb39ef632007-03-08 10:06:09 +0100971#ifdef CONFIG_DDR_ECC
York Sun4a598092013-04-01 11:29:11 -0700972 ecc_enabled = true;
Stefan Roeseb39ef632007-03-08 10:06:09 +0100973#else
York Sun4a598092013-04-01 11:29:11 -0700974 ecc_enabled = false;
Stefan Roeseb39ef632007-03-08 10:06:09 +0100975#endif
York Sun4a598092013-04-01 11:29:11 -0700976 dimm_32bit = false;
977 dimm_64bit = false;
978 buf0 = false;
979 buf1 = false;
Stefan Roese43f32472007-02-20 10:43:34 +0100980
981 /*------------------------------------------------------------------
982 * Set memory controller options reg 1, SDRAM_MCOPT1.
983 *-----------------------------------------------------------------*/
984 mfsdram(SDRAM_MCOPT1, val);
985 mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
986 SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK |
987 SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
988 SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
989 SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
990 SDRAM_MCOPT1_DREF_MASK);
991
992 mcopt1 |= SDRAM_MCOPT1_QDEP;
993 mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
994 mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
995 mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
996 mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
997 mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
998
999 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1000 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1001 /* test ecc support */
1002 ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
1003 if (ecc != 0x02) /* ecc not supported */
York Sun4a598092013-04-01 11:29:11 -07001004 ecc_enabled = false;
Stefan Roese43f32472007-02-20 10:43:34 +01001005
1006 /* test bank count */
1007 bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
1008 if (bankcount == 0x04) /* bank count = 4 */
1009 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
1010 else /* bank count = 8 */
1011 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
1012
Stefan Roese43f32472007-02-20 10:43:34 +01001013 /* test for buffered/unbuffered, registered, differential clocks */
1014 registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
1015 attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
1016
1017 /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1018 if (dimm_num == 0) {
1019 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1020 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1021 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1022 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1023 if (registered == 1) { /* DDR2 always buffered */
1024 /* TODO: what about above comments ? */
1025 mcopt1 |= SDRAM_MCOPT1_RDEN;
York Sun4a598092013-04-01 11:29:11 -07001026 buf0 = true;
Stefan Roese43f32472007-02-20 10:43:34 +01001027 } else {
1028 /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1029 if ((attribute & 0x02) == 0x00) {
1030 /* buffered not supported */
York Sun4a598092013-04-01 11:29:11 -07001031 buf0 = false;
Stefan Roese43f32472007-02-20 10:43:34 +01001032 } else {
1033 mcopt1 |= SDRAM_MCOPT1_RDEN;
York Sun4a598092013-04-01 11:29:11 -07001034 buf0 = true;
Stefan Roese43f32472007-02-20 10:43:34 +01001035 }
1036 }
1037 }
1038 else if (dimm_num == 1) {
1039 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1040 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1041 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1042 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1043 if (registered == 1) {
1044 /* DDR2 always buffered */
1045 mcopt1 |= SDRAM_MCOPT1_RDEN;
York Sun4a598092013-04-01 11:29:11 -07001046 buf1 = true;
Stefan Roese43f32472007-02-20 10:43:34 +01001047 } else {
1048 if ((attribute & 0x02) == 0x00) {
1049 /* buffered not supported */
York Sun4a598092013-04-01 11:29:11 -07001050 buf1 = false;
Stefan Roese43f32472007-02-20 10:43:34 +01001051 } else {
1052 mcopt1 |= SDRAM_MCOPT1_RDEN;
York Sun4a598092013-04-01 11:29:11 -07001053 buf1 = true;
Stefan Roese43f32472007-02-20 10:43:34 +01001054 }
1055 }
1056 }
1057
1058 /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1059 data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1060 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1061
1062 switch (data_width) {
1063 case 72:
1064 case 64:
York Sun4a598092013-04-01 11:29:11 -07001065 dimm_64bit = true;
Stefan Roese43f32472007-02-20 10:43:34 +01001066 break;
1067 case 40:
1068 case 32:
York Sun4a598092013-04-01 11:29:11 -07001069 dimm_32bit = true;
Stefan Roese43f32472007-02-20 10:43:34 +01001070 break;
1071 default:
Stefan Roese251161b2008-07-10 09:58:06 +02001072 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
Stefan Roese43f32472007-02-20 10:43:34 +01001073 data_width);
1074 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1075 break;
1076 }
1077 }
1078 }
1079
1080 /* verify matching properties */
1081 if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1082 if (buf0 != buf1) {
1083 printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
Heiko Schocher68310b02007-06-25 19:11:37 +02001084 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +01001085 }
1086 }
1087
York Sun4a598092013-04-01 11:29:11 -07001088 if ((dimm_64bit == true) && (dimm_32bit == true)) {
Stefan Roese43f32472007-02-20 10:43:34 +01001089 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
Heiko Schocher68310b02007-06-25 19:11:37 +02001090 spd_ddr_init_hang ();
York Sun4a598092013-04-01 11:29:11 -07001091 } else if ((dimm_64bit == true) && (dimm_32bit == false)) {
Stefan Roese43f32472007-02-20 10:43:34 +01001092 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
York Sun4a598092013-04-01 11:29:11 -07001093 } else if ((dimm_64bit == false) && (dimm_32bit == true)) {
Stefan Roese43f32472007-02-20 10:43:34 +01001094 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1095 } else {
1096 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
Heiko Schocher68310b02007-06-25 19:11:37 +02001097 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +01001098 }
1099
York Sun4a598092013-04-01 11:29:11 -07001100 if (ecc_enabled == true)
Stefan Roese43f32472007-02-20 10:43:34 +01001101 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1102 else
1103 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1104
1105 mtsdram(SDRAM_MCOPT1, mcopt1);
1106}
1107
1108/*-----------------------------------------------------------------------------+
1109 * program_codt.
1110 *-----------------------------------------------------------------------------*/
1111static void program_codt(unsigned long *dimm_populated,
1112 unsigned char *iic0_dimm_addr,
1113 unsigned long num_dimm_banks)
1114{
1115 unsigned long codt;
1116 unsigned long modt0 = 0;
1117 unsigned long modt1 = 0;
1118 unsigned long modt2 = 0;
1119 unsigned long modt3 = 0;
1120 unsigned char dimm_num;
1121 unsigned char dimm_rank;
1122 unsigned char total_rank = 0;
1123 unsigned char total_dimm = 0;
1124 unsigned char dimm_type = 0;
1125 unsigned char firstSlot = 0;
1126
1127 /*------------------------------------------------------------------
1128 * Set the SDRAM Controller On Die Termination Register
1129 *-----------------------------------------------------------------*/
1130 mfsdram(SDRAM_CODT, codt);
Carolyn Smith5b648422009-02-12 06:13:44 +01001131 codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END);
1132 codt |= SDRAM_CODT_IO_NMODE;
Stefan Roese43f32472007-02-20 10:43:34 +01001133
1134 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1135 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1136 dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1137 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1138 dimm_rank = (dimm_rank & 0x0F) + 1;
1139 dimm_type = SDRAM_DDR2;
1140 } else {
1141 dimm_rank = dimm_rank & 0x0F;
1142 dimm_type = SDRAM_DDR1;
1143 }
1144
Stefan Roesebad41112007-03-01 21:11:36 +01001145 total_rank += dimm_rank;
1146 total_dimm++;
Stefan Roese43f32472007-02-20 10:43:34 +01001147 if ((dimm_num == 0) && (total_dimm == 1))
York Sun4a598092013-04-01 11:29:11 -07001148 firstSlot = true;
Stefan Roese43f32472007-02-20 10:43:34 +01001149 else
York Sun4a598092013-04-01 11:29:11 -07001150 firstSlot = false;
Stefan Roese43f32472007-02-20 10:43:34 +01001151 }
1152 }
1153 if (dimm_type == SDRAM_DDR2) {
1154 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
York Sun4a598092013-04-01 11:29:11 -07001155 if ((total_dimm == 1) && (firstSlot == true)) {
Stefan Roese37628252008-08-06 14:05:38 +02001156 if (total_rank == 1) { /* PUUU */
Stefan Roesebad41112007-03-01 21:11:36 +01001157 codt |= CALC_ODT_R(0);
1158 modt0 = CALC_ODT_W(0);
Stefan Roese43f32472007-02-20 10:43:34 +01001159 modt1 = 0x00000000;
1160 modt2 = 0x00000000;
1161 modt3 = 0x00000000;
1162 }
Stefan Roese37628252008-08-06 14:05:38 +02001163 if (total_rank == 2) { /* PPUU */
Stefan Roesebad41112007-03-01 21:11:36 +01001164 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
Stefan Roese37628252008-08-06 14:05:38 +02001165 modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
1166 modt1 = 0x00000000;
Stefan Roese43f32472007-02-20 10:43:34 +01001167 modt2 = 0x00000000;
1168 modt3 = 0x00000000;
1169 }
York Sun4a598092013-04-01 11:29:11 -07001170 } else if ((total_dimm == 1) && (firstSlot != true)) {
Stefan Roese37628252008-08-06 14:05:38 +02001171 if (total_rank == 1) { /* UUPU */
Stefan Roesebad41112007-03-01 21:11:36 +01001172 codt |= CALC_ODT_R(2);
1173 modt0 = 0x00000000;
Stefan Roese43f32472007-02-20 10:43:34 +01001174 modt1 = 0x00000000;
Stefan Roesebad41112007-03-01 21:11:36 +01001175 modt2 = CALC_ODT_W(2);
Stefan Roese43f32472007-02-20 10:43:34 +01001176 modt3 = 0x00000000;
1177 }
Stefan Roese37628252008-08-06 14:05:38 +02001178 if (total_rank == 2) { /* UUPP */
Stefan Roesebad41112007-03-01 21:11:36 +01001179 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1180 modt0 = 0x00000000;
1181 modt1 = 0x00000000;
Stefan Roese37628252008-08-06 14:05:38 +02001182 modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
1183 modt3 = 0x00000000;
Stefan Roese43f32472007-02-20 10:43:34 +01001184 }
1185 }
1186 if (total_dimm == 2) {
Stefan Roese37628252008-08-06 14:05:38 +02001187 if (total_rank == 2) { /* PUPU */
Stefan Roesebad41112007-03-01 21:11:36 +01001188 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1189 modt0 = CALC_ODT_RW(2);
Stefan Roese43f32472007-02-20 10:43:34 +01001190 modt1 = 0x00000000;
Stefan Roesebad41112007-03-01 21:11:36 +01001191 modt2 = CALC_ODT_RW(0);
Stefan Roese43f32472007-02-20 10:43:34 +01001192 modt3 = 0x00000000;
1193 }
Stefan Roese37628252008-08-06 14:05:38 +02001194 if (total_rank == 4) { /* PPPP */
Stefan Roese32a1cad2007-06-01 13:45:00 +02001195 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1196 CALC_ODT_R(2) | CALC_ODT_R(3);
Stefan Roese37628252008-08-06 14:05:38 +02001197 modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
Stefan Roesebad41112007-03-01 21:11:36 +01001198 modt1 = 0x00000000;
Stefan Roese37628252008-08-06 14:05:38 +02001199 modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
Stefan Roesebad41112007-03-01 21:11:36 +01001200 modt3 = 0x00000000;
Stefan Roese43f32472007-02-20 10:43:34 +01001201 }
1202 }
Wolfgang Denkf972e772007-03-04 01:36:05 +01001203 } else {
Stefan Roese43f32472007-02-20 10:43:34 +01001204 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1205 modt0 = 0x00000000;
1206 modt1 = 0x00000000;
1207 modt2 = 0x00000000;
1208 modt3 = 0x00000000;
1209
1210 if (total_dimm == 1) {
1211 if (total_rank == 1)
1212 codt |= 0x00800000;
1213 if (total_rank == 2)
1214 codt |= 0x02800000;
1215 }
1216 if (total_dimm == 2) {
1217 if (total_rank == 2)
1218 codt |= 0x08800000;
1219 if (total_rank == 4)
1220 codt |= 0x2a800000;
1221 }
1222 }
1223
1224 debug("nb of dimm %d\n", total_dimm);
1225 debug("nb of rank %d\n", total_rank);
1226 if (total_dimm == 1)
1227 debug("dimm in slot %d\n", firstSlot);
1228
1229 mtsdram(SDRAM_CODT, codt);
1230 mtsdram(SDRAM_MODT0, modt0);
1231 mtsdram(SDRAM_MODT1, modt1);
1232 mtsdram(SDRAM_MODT2, modt2);
1233 mtsdram(SDRAM_MODT3, modt3);
1234}
1235
1236/*-----------------------------------------------------------------------------+
1237 * program_initplr.
1238 *-----------------------------------------------------------------------------*/
1239static void program_initplr(unsigned long *dimm_populated,
1240 unsigned char *iic0_dimm_addr,
1241 unsigned long num_dimm_banks,
Wolfgang Denkb38e0df2007-03-06 18:08:43 +01001242 ddr_cas_id_t selected_cas,
Stefan Roesebad41112007-03-01 21:11:36 +01001243 int write_recovery)
Stefan Roese43f32472007-02-20 10:43:34 +01001244{
Stefan Roesebad41112007-03-01 21:11:36 +01001245 u32 cas = 0;
1246 u32 odt = 0;
1247 u32 ods = 0;
1248 u32 mr;
1249 u32 wr;
1250 u32 emr;
1251 u32 emr2;
1252 u32 emr3;
1253 int dimm_num;
1254 int total_dimm = 0;
Stefan Roese43f32472007-02-20 10:43:34 +01001255
1256 /******************************************************
1257 ** Assumption: if more than one DIMM, all DIMMs are the same
Wolfgang Denk52232fd2007-02-27 14:26:04 +01001258 ** as already checked in check_memory_type
Stefan Roese43f32472007-02-20 10:43:34 +01001259 ******************************************************/
1260
1261 if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1262 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1263 mtsdram(SDRAM_INITPLR1, 0x81900400);
1264 mtsdram(SDRAM_INITPLR2, 0x81810000);
1265 mtsdram(SDRAM_INITPLR3, 0xff800162);
1266 mtsdram(SDRAM_INITPLR4, 0x81900400);
1267 mtsdram(SDRAM_INITPLR5, 0x86080000);
1268 mtsdram(SDRAM_INITPLR6, 0x86080000);
1269 mtsdram(SDRAM_INITPLR7, 0x81000062);
1270 } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1271 switch (selected_cas) {
Stefan Roese43f32472007-02-20 10:43:34 +01001272 case DDR_CAS_3:
Stefan Roesebad41112007-03-01 21:11:36 +01001273 cas = 3 << 4;
Stefan Roese43f32472007-02-20 10:43:34 +01001274 break;
1275 case DDR_CAS_4:
Stefan Roesebad41112007-03-01 21:11:36 +01001276 cas = 4 << 4;
Stefan Roese43f32472007-02-20 10:43:34 +01001277 break;
1278 case DDR_CAS_5:
Stefan Roesebad41112007-03-01 21:11:36 +01001279 cas = 5 << 4;
1280 break;
1281 default:
1282 printf("ERROR: ucode error on selected_cas value %d", selected_cas);
Heiko Schocher68310b02007-06-25 19:11:37 +02001283 spd_ddr_init_hang ();
Stefan Roesebad41112007-03-01 21:11:36 +01001284 break;
1285 }
1286
1287#if 0
1288 /*
1289 * ToDo - Still a problem with the write recovery:
1290 * On the Corsair CM2X512-5400C4 module, setting write recovery
1291 * in the INITPLR reg to the value calculated in program_mode()
1292 * results in not correctly working DDR2 memory (crash after
1293 * relocation).
1294 *
1295 * So for now, set the write recovery to 3. This seems to work
1296 * on the Corair module too.
1297 *
1298 * 2007-03-01, sr
1299 */
1300 switch (write_recovery) {
1301 case 3:
1302 wr = WRITE_RECOV_3;
1303 break;
1304 case 4:
1305 wr = WRITE_RECOV_4;
1306 break;
1307 case 5:
1308 wr = WRITE_RECOV_5;
1309 break;
1310 case 6:
1311 wr = WRITE_RECOV_6;
Stefan Roese43f32472007-02-20 10:43:34 +01001312 break;
1313 default:
Stefan Roesebad41112007-03-01 21:11:36 +01001314 printf("ERROR: write recovery not support (%d)", write_recovery);
Heiko Schocher68310b02007-06-25 19:11:37 +02001315 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +01001316 break;
1317 }
Stefan Roesebad41112007-03-01 21:11:36 +01001318#else
1319 wr = WRITE_RECOV_3; /* test-only, see description above */
1320#endif
1321
1322 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1323 if (dimm_populated[dimm_num] != SDRAM_NONE)
1324 total_dimm++;
1325 if (total_dimm == 1) {
1326 odt = ODT_150_OHM;
1327 ods = ODS_FULL;
1328 } else if (total_dimm == 2) {
1329 odt = ODT_75_OHM;
1330 ods = ODS_REDUCED;
1331 } else {
1332 printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
Heiko Schocher68310b02007-06-25 19:11:37 +02001333 spd_ddr_init_hang ();
Stefan Roesebad41112007-03-01 21:11:36 +01001334 }
Stefan Roese43f32472007-02-20 10:43:34 +01001335
Stefan Roesebad41112007-03-01 21:11:36 +01001336 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1337 emr = CMD_EMR | SELECT_EMR | odt | ods;
1338 emr2 = CMD_EMR | SELECT_EMR2;
1339 emr3 = CMD_EMR | SELECT_EMR3;
Prodyut Hazarika52b6bec2008-08-27 16:39:00 -07001340 /* NOP - Wait 106 MemClk cycles */
1341 mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
1342 SDRAM_INITPLR_IMWT_ENCODE(106));
Stefan Roesebad41112007-03-01 21:11:36 +01001343 udelay(1000);
Prodyut Hazarika52b6bec2008-08-27 16:39:00 -07001344 /* precharge 4 MemClk cycles */
1345 mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1346 SDRAM_INITPLR_IMWT_ENCODE(4));
1347 /* EMR2 - Wait tMRD (2 MemClk cycles) */
1348 mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
1349 SDRAM_INITPLR_IMWT_ENCODE(2));
1350 /* EMR3 - Wait tMRD (2 MemClk cycles) */
1351 mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
1352 SDRAM_INITPLR_IMWT_ENCODE(2));
1353 /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
1354 mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
1355 SDRAM_INITPLR_IMWT_ENCODE(2));
1356 /* MR w/ DLL reset - 200 cycle wait for DLL reset */
1357 mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
1358 SDRAM_INITPLR_IMWT_ENCODE(200));
Stefan Roesebad41112007-03-01 21:11:36 +01001359 udelay(1000);
Prodyut Hazarika52b6bec2008-08-27 16:39:00 -07001360 /* precharge 4 MemClk cycles */
1361 mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1362 SDRAM_INITPLR_IMWT_ENCODE(4));
1363 /* Refresh 25 MemClk cycles */
1364 mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1365 SDRAM_INITPLR_IMWT_ENCODE(25));
1366 /* Refresh 25 MemClk cycles */
1367 mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1368 SDRAM_INITPLR_IMWT_ENCODE(25));
1369 /* Refresh 25 MemClk cycles */
1370 mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1371 SDRAM_INITPLR_IMWT_ENCODE(25));
1372 /* Refresh 25 MemClk cycles */
1373 mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1374 SDRAM_INITPLR_IMWT_ENCODE(25));
1375 /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
1376 mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
1377 SDRAM_INITPLR_IMWT_ENCODE(2));
1378 /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
1379 mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
1380 SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
1381 /* EMR OCD Exit */
1382 mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
1383 SDRAM_INITPLR_IMWT_ENCODE(2));
Stefan Roese43f32472007-02-20 10:43:34 +01001384 } else {
1385 printf("ERROR: ucode error as unknown DDR type in program_initplr");
Heiko Schocher68310b02007-06-25 19:11:37 +02001386 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +01001387 }
1388}
1389
1390/*------------------------------------------------------------------
1391 * This routine programs the SDRAM_MMODE register.
1392 * the selected_cas is an output parameter, that will be passed
1393 * by caller to call the above program_initplr( )
1394 *-----------------------------------------------------------------*/
1395static void program_mode(unsigned long *dimm_populated,
1396 unsigned char *iic0_dimm_addr,
1397 unsigned long num_dimm_banks,
Stefan Roesebad41112007-03-01 21:11:36 +01001398 ddr_cas_id_t *selected_cas,
1399 int *write_recovery)
Stefan Roese43f32472007-02-20 10:43:34 +01001400{
1401 unsigned long dimm_num;
1402 unsigned long sdram_ddr1;
1403 unsigned long t_wr_ns;
1404 unsigned long t_wr_clk;
1405 unsigned long cas_bit;
1406 unsigned long cas_index;
1407 unsigned long sdram_freq;
1408 unsigned long ddr_check;
1409 unsigned long mmode;
1410 unsigned long tcyc_reg;
1411 unsigned long cycle_2_0_clk;
1412 unsigned long cycle_2_5_clk;
1413 unsigned long cycle_3_0_clk;
1414 unsigned long cycle_4_0_clk;
1415 unsigned long cycle_5_0_clk;
1416 unsigned long max_2_0_tcyc_ns_x_100;
1417 unsigned long max_2_5_tcyc_ns_x_100;
1418 unsigned long max_3_0_tcyc_ns_x_100;
1419 unsigned long max_4_0_tcyc_ns_x_100;
1420 unsigned long max_5_0_tcyc_ns_x_100;
1421 unsigned long cycle_time_ns_x_100[3];
Stefan Roeseedd73f22007-10-21 08:12:41 +02001422 PPC4xx_SYS_INFO board_cfg;
Stefan Roese43f32472007-02-20 10:43:34 +01001423 unsigned char cas_2_0_available;
1424 unsigned char cas_2_5_available;
1425 unsigned char cas_3_0_available;
1426 unsigned char cas_4_0_available;
1427 unsigned char cas_5_0_available;
1428 unsigned long sdr_ddrpll;
1429
1430 /*------------------------------------------------------------------
1431 * Get the board configuration info.
1432 *-----------------------------------------------------------------*/
1433 get_sys_info(&board_cfg);
1434
Stefan Roeseb39ef632007-03-08 10:06:09 +01001435 mfsdr(SDR0_DDR0, sdr_ddrpll);
Stefan Roese43f32472007-02-20 10:43:34 +01001436 sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
Felix Radensky8d4d4a62009-07-01 11:37:46 +03001437 debug("sdram_freq=%lu\n", sdram_freq);
Stefan Roese43f32472007-02-20 10:43:34 +01001438
1439 /*------------------------------------------------------------------
1440 * Handle the timing. We need to find the worst case timing of all
1441 * the dimm modules installed.
1442 *-----------------------------------------------------------------*/
1443 t_wr_ns = 0;
York Sun4a598092013-04-01 11:29:11 -07001444 cas_2_0_available = true;
1445 cas_2_5_available = true;
1446 cas_3_0_available = true;
1447 cas_4_0_available = true;
1448 cas_5_0_available = true;
Stefan Roese43f32472007-02-20 10:43:34 +01001449 max_2_0_tcyc_ns_x_100 = 10;
1450 max_2_5_tcyc_ns_x_100 = 10;
1451 max_3_0_tcyc_ns_x_100 = 10;
1452 max_4_0_tcyc_ns_x_100 = 10;
1453 max_5_0_tcyc_ns_x_100 = 10;
York Sun4a598092013-04-01 11:29:11 -07001454 sdram_ddr1 = true;
Stefan Roese43f32472007-02-20 10:43:34 +01001455
1456 /* loop through all the DIMM slots on the board */
1457 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1458 /* If a dimm is installed in a particular slot ... */
1459 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1460 if (dimm_populated[dimm_num] == SDRAM_DDR1)
York Sun4a598092013-04-01 11:29:11 -07001461 sdram_ddr1 = true;
Stefan Roese43f32472007-02-20 10:43:34 +01001462 else
York Sun4a598092013-04-01 11:29:11 -07001463 sdram_ddr1 = false;
Stefan Roese43f32472007-02-20 10:43:34 +01001464
Stefan Roese43f32472007-02-20 10:43:34 +01001465 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
Felix Radensky8d4d4a62009-07-01 11:37:46 +03001466 debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
Stefan Roese43f32472007-02-20 10:43:34 +01001467
1468 /* For a particular DIMM, grab the three CAS values it supports */
1469 for (cas_index = 0; cas_index < 3; cas_index++) {
1470 switch (cas_index) {
1471 case 0:
1472 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1473 break;
1474 case 1:
1475 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1476 break;
1477 default:
1478 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1479 break;
1480 }
1481
1482 if ((tcyc_reg & 0x0F) >= 10) {
1483 if ((tcyc_reg & 0x0F) == 0x0D) {
1484 /* Convert from hex to decimal */
Stefan Roese5d48a842007-03-31 13:15:06 +02001485 cycle_time_ns_x_100[cas_index] =
1486 (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
Stefan Roese43f32472007-02-20 10:43:34 +01001487 } else {
1488 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1489 "in slot %d\n", (unsigned int)dimm_num);
Heiko Schocher68310b02007-06-25 19:11:37 +02001490 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +01001491 }
1492 } else {
1493 /* Convert from hex to decimal */
Stefan Roese5d48a842007-03-31 13:15:06 +02001494 cycle_time_ns_x_100[cas_index] =
1495 (((tcyc_reg & 0xF0) >> 4) * 100) +
Stefan Roese43f32472007-02-20 10:43:34 +01001496 ((tcyc_reg & 0x0F)*10);
1497 }
Felix Radensky8d4d4a62009-07-01 11:37:46 +03001498 debug("cas_index=%lu: cycle_time_ns_x_100=%lu\n", cas_index,
Stefan Roese5d48a842007-03-31 13:15:06 +02001499 cycle_time_ns_x_100[cas_index]);
Stefan Roese43f32472007-02-20 10:43:34 +01001500 }
1501
1502 /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1503 /* supported for a particular DIMM. */
1504 cas_index = 0;
1505
1506 if (sdram_ddr1) {
1507 /*
1508 * DDR devices use the following bitmask for CAS latency:
1509 * Bit 7 6 5 4 3 2 1 0
1510 * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0
1511 */
Stefan Roese5d48a842007-03-31 13:15:06 +02001512 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1513 (cycle_time_ns_x_100[cas_index] != 0)) {
1514 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1515 cycle_time_ns_x_100[cas_index]);
Stefan Roese43f32472007-02-20 10:43:34 +01001516 cas_index++;
1517 } else {
1518 if (cas_index != 0)
1519 cas_index++;
York Sun4a598092013-04-01 11:29:11 -07001520 cas_4_0_available = false;
Stefan Roese43f32472007-02-20 10:43:34 +01001521 }
1522
Stefan Roese5d48a842007-03-31 13:15:06 +02001523 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1524 (cycle_time_ns_x_100[cas_index] != 0)) {
1525 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1526 cycle_time_ns_x_100[cas_index]);
Stefan Roese43f32472007-02-20 10:43:34 +01001527 cas_index++;
1528 } else {
1529 if (cas_index != 0)
1530 cas_index++;
York Sun4a598092013-04-01 11:29:11 -07001531 cas_3_0_available = false;
Stefan Roese43f32472007-02-20 10:43:34 +01001532 }
1533
Stefan Roese5d48a842007-03-31 13:15:06 +02001534 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1535 (cycle_time_ns_x_100[cas_index] != 0)) {
1536 max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1537 cycle_time_ns_x_100[cas_index]);
Stefan Roese43f32472007-02-20 10:43:34 +01001538 cas_index++;
1539 } else {
1540 if (cas_index != 0)
1541 cas_index++;
York Sun4a598092013-04-01 11:29:11 -07001542 cas_2_5_available = false;
Stefan Roese43f32472007-02-20 10:43:34 +01001543 }
1544
Stefan Roese5d48a842007-03-31 13:15:06 +02001545 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1546 (cycle_time_ns_x_100[cas_index] != 0)) {
1547 max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1548 cycle_time_ns_x_100[cas_index]);
Stefan Roese43f32472007-02-20 10:43:34 +01001549 cas_index++;
1550 } else {
1551 if (cas_index != 0)
1552 cas_index++;
York Sun4a598092013-04-01 11:29:11 -07001553 cas_2_0_available = false;
Stefan Roese43f32472007-02-20 10:43:34 +01001554 }
1555 } else {
1556 /*
1557 * DDR2 devices use the following bitmask for CAS latency:
1558 * Bit 7 6 5 4 3 2 1 0
1559 * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
1560 */
Stefan Roese5d48a842007-03-31 13:15:06 +02001561 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1562 (cycle_time_ns_x_100[cas_index] != 0)) {
1563 max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1564 cycle_time_ns_x_100[cas_index]);
Stefan Roese43f32472007-02-20 10:43:34 +01001565 cas_index++;
1566 } else {
1567 if (cas_index != 0)
1568 cas_index++;
York Sun4a598092013-04-01 11:29:11 -07001569 cas_5_0_available = false;
Stefan Roese43f32472007-02-20 10:43:34 +01001570 }
1571
Stefan Roese5d48a842007-03-31 13:15:06 +02001572 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1573 (cycle_time_ns_x_100[cas_index] != 0)) {
1574 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1575 cycle_time_ns_x_100[cas_index]);
Stefan Roese43f32472007-02-20 10:43:34 +01001576 cas_index++;
1577 } else {
1578 if (cas_index != 0)
1579 cas_index++;
York Sun4a598092013-04-01 11:29:11 -07001580 cas_4_0_available = false;
Stefan Roese43f32472007-02-20 10:43:34 +01001581 }
1582
Stefan Roese5d48a842007-03-31 13:15:06 +02001583 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1584 (cycle_time_ns_x_100[cas_index] != 0)) {
1585 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1586 cycle_time_ns_x_100[cas_index]);
Stefan Roese43f32472007-02-20 10:43:34 +01001587 cas_index++;
1588 } else {
1589 if (cas_index != 0)
1590 cas_index++;
York Sun4a598092013-04-01 11:29:11 -07001591 cas_3_0_available = false;
Stefan Roese43f32472007-02-20 10:43:34 +01001592 }
1593 }
1594 }
1595 }
1596
1597 /*------------------------------------------------------------------
1598 * Set the SDRAM mode, SDRAM_MMODE
1599 *-----------------------------------------------------------------*/
1600 mfsdram(SDRAM_MMODE, mmode);
1601 mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1602
Stefan Roeseb39ef632007-03-08 10:06:09 +01001603 /* add 10 here because of rounding problems */
1604 cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1605 cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1606 cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1607 cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1608 cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
Felix Radensky8d4d4a62009-07-01 11:37:46 +03001609 debug("cycle_3_0_clk=%lu\n", cycle_3_0_clk);
1610 debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk);
1611 debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk);
Stefan Roese43f32472007-02-20 10:43:34 +01001612
York Sun4a598092013-04-01 11:29:11 -07001613 if (sdram_ddr1 == true) { /* DDR1 */
1614 if ((cas_2_0_available == true) &&
1615 (sdram_freq <= cycle_2_0_clk)) {
Stefan Roese43f32472007-02-20 10:43:34 +01001616 mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1617 *selected_cas = DDR_CAS_2;
York Sun4a598092013-04-01 11:29:11 -07001618 } else if ((cas_2_5_available == true) &&
1619 (sdram_freq <= cycle_2_5_clk)) {
Stefan Roese43f32472007-02-20 10:43:34 +01001620 mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1621 *selected_cas = DDR_CAS_2_5;
York Sun4a598092013-04-01 11:29:11 -07001622 } else if ((cas_3_0_available == true) &&
1623 (sdram_freq <= cycle_3_0_clk)) {
Stefan Roese43f32472007-02-20 10:43:34 +01001624 mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1625 *selected_cas = DDR_CAS_3;
1626 } else {
1627 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1628 printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1629 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
Heiko Schocher68310b02007-06-25 19:11:37 +02001630 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +01001631 }
1632 } else { /* DDR2 */
Stefan Roesef88e3602007-03-31 08:46:08 +02001633 debug("cas_3_0_available=%d\n", cas_3_0_available);
1634 debug("cas_4_0_available=%d\n", cas_4_0_available);
1635 debug("cas_5_0_available=%d\n", cas_5_0_available);
York Sun4a598092013-04-01 11:29:11 -07001636 if ((cas_3_0_available == true) &&
1637 (sdram_freq <= cycle_3_0_clk)) {
Stefan Roese43f32472007-02-20 10:43:34 +01001638 mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1639 *selected_cas = DDR_CAS_3;
York Sun4a598092013-04-01 11:29:11 -07001640 } else if ((cas_4_0_available == true) &&
1641 (sdram_freq <= cycle_4_0_clk)) {
Stefan Roese43f32472007-02-20 10:43:34 +01001642 mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1643 *selected_cas = DDR_CAS_4;
York Sun4a598092013-04-01 11:29:11 -07001644 } else if ((cas_5_0_available == true) &&
1645 (sdram_freq <= cycle_5_0_clk)) {
Stefan Roese43f32472007-02-20 10:43:34 +01001646 mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1647 *selected_cas = DDR_CAS_5;
1648 } else {
1649 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1650 printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
Stefan Roeseb39ef632007-03-08 10:06:09 +01001651 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1652 printf("cas3=%d cas4=%d cas5=%d\n",
1653 cas_3_0_available, cas_4_0_available, cas_5_0_available);
Stefan Roese251161b2008-07-10 09:58:06 +02001654 printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
Stefan Roeseb39ef632007-03-08 10:06:09 +01001655 sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
Heiko Schocher68310b02007-06-25 19:11:37 +02001656 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +01001657 }
1658 }
1659
York Sun4a598092013-04-01 11:29:11 -07001660 if (sdram_ddr1 == true)
Stefan Roese43f32472007-02-20 10:43:34 +01001661 mmode |= SDRAM_MMODE_WR_DDR1;
1662 else {
1663
1664 /* loop through all the DIMM slots on the board */
1665 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1666 /* If a dimm is installed in a particular slot ... */
1667 if (dimm_populated[dimm_num] != SDRAM_NONE)
1668 t_wr_ns = max(t_wr_ns,
1669 spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1670 }
1671
1672 /*
1673 * convert from nanoseconds to ddr clocks
1674 * round up if necessary
1675 */
1676 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1677 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1678 if (sdram_freq != ddr_check)
1679 t_wr_clk++;
1680
1681 switch (t_wr_clk) {
1682 case 0:
1683 case 1:
1684 case 2:
1685 case 3:
1686 mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1687 break;
1688 case 4:
1689 mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1690 break;
1691 case 5:
1692 mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1693 break;
1694 default:
1695 mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1696 break;
1697 }
Stefan Roesebad41112007-03-01 21:11:36 +01001698 *write_recovery = t_wr_clk;
Stefan Roese43f32472007-02-20 10:43:34 +01001699 }
1700
Stefan Roesebad41112007-03-01 21:11:36 +01001701 debug("CAS latency = %d\n", *selected_cas);
1702 debug("Write recovery = %d\n", *write_recovery);
1703
Stefan Roese43f32472007-02-20 10:43:34 +01001704 mtsdram(SDRAM_MMODE, mmode);
1705}
1706
1707/*-----------------------------------------------------------------------------+
1708 * program_rtr.
1709 *-----------------------------------------------------------------------------*/
1710static void program_rtr(unsigned long *dimm_populated,
1711 unsigned char *iic0_dimm_addr,
1712 unsigned long num_dimm_banks)
1713{
Stefan Roeseedd73f22007-10-21 08:12:41 +02001714 PPC4xx_SYS_INFO board_cfg;
Stefan Roese43f32472007-02-20 10:43:34 +01001715 unsigned long max_refresh_rate;
1716 unsigned long dimm_num;
1717 unsigned long refresh_rate_type;
1718 unsigned long refresh_rate;
1719 unsigned long rint;
1720 unsigned long sdram_freq;
1721 unsigned long sdr_ddrpll;
1722 unsigned long val;
1723
1724 /*------------------------------------------------------------------
1725 * Get the board configuration info.
1726 *-----------------------------------------------------------------*/
1727 get_sys_info(&board_cfg);
1728
1729 /*------------------------------------------------------------------
1730 * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1731 *-----------------------------------------------------------------*/
Stefan Roeseb39ef632007-03-08 10:06:09 +01001732 mfsdr(SDR0_DDR0, sdr_ddrpll);
Stefan Roese43f32472007-02-20 10:43:34 +01001733 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1734
1735 max_refresh_rate = 0;
1736 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1737 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1738
1739 refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1740 refresh_rate_type &= 0x7F;
1741 switch (refresh_rate_type) {
1742 case 0:
1743 refresh_rate = 15625;
1744 break;
1745 case 1:
1746 refresh_rate = 3906;
1747 break;
1748 case 2:
1749 refresh_rate = 7812;
1750 break;
1751 case 3:
1752 refresh_rate = 31250;
1753 break;
1754 case 4:
1755 refresh_rate = 62500;
1756 break;
1757 case 5:
1758 refresh_rate = 125000;
1759 break;
1760 default:
1761 refresh_rate = 0;
1762 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1763 (unsigned int)dimm_num);
1764 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schocher68310b02007-06-25 19:11:37 +02001765 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +01001766 break;
1767 }
1768
1769 max_refresh_rate = max(max_refresh_rate, refresh_rate);
1770 }
1771 }
1772
1773 rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1774 mfsdram(SDRAM_RTR, val);
1775 mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1776 (SDRAM_RTR_RINT_ENCODE(rint)));
1777}
1778
1779/*------------------------------------------------------------------
1780 * This routine programs the SDRAM_TRx registers.
1781 *-----------------------------------------------------------------*/
1782static void program_tr(unsigned long *dimm_populated,
1783 unsigned char *iic0_dimm_addr,
1784 unsigned long num_dimm_banks)
1785{
1786 unsigned long dimm_num;
1787 unsigned long sdram_ddr1;
1788 unsigned long t_rp_ns;
1789 unsigned long t_rcd_ns;
1790 unsigned long t_rrd_ns;
1791 unsigned long t_ras_ns;
1792 unsigned long t_rc_ns;
1793 unsigned long t_rfc_ns;
1794 unsigned long t_wpc_ns;
1795 unsigned long t_wtr_ns;
1796 unsigned long t_rpc_ns;
1797 unsigned long t_rp_clk;
1798 unsigned long t_rcd_clk;
1799 unsigned long t_rrd_clk;
1800 unsigned long t_ras_clk;
1801 unsigned long t_rc_clk;
1802 unsigned long t_rfc_clk;
1803 unsigned long t_wpc_clk;
1804 unsigned long t_wtr_clk;
1805 unsigned long t_rpc_clk;
1806 unsigned long sdtr1, sdtr2, sdtr3;
1807 unsigned long ddr_check;
1808 unsigned long sdram_freq;
1809 unsigned long sdr_ddrpll;
1810
Stefan Roeseedd73f22007-10-21 08:12:41 +02001811 PPC4xx_SYS_INFO board_cfg;
Stefan Roese43f32472007-02-20 10:43:34 +01001812
1813 /*------------------------------------------------------------------
1814 * Get the board configuration info.
1815 *-----------------------------------------------------------------*/
1816 get_sys_info(&board_cfg);
1817
Stefan Roeseb39ef632007-03-08 10:06:09 +01001818 mfsdr(SDR0_DDR0, sdr_ddrpll);
Stefan Roese43f32472007-02-20 10:43:34 +01001819 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1820
1821 /*------------------------------------------------------------------
1822 * Handle the timing. We need to find the worst case timing of all
1823 * the dimm modules installed.
1824 *-----------------------------------------------------------------*/
1825 t_rp_ns = 0;
1826 t_rrd_ns = 0;
1827 t_rcd_ns = 0;
1828 t_ras_ns = 0;
1829 t_rc_ns = 0;
1830 t_rfc_ns = 0;
1831 t_wpc_ns = 0;
1832 t_wtr_ns = 0;
1833 t_rpc_ns = 0;
York Sun4a598092013-04-01 11:29:11 -07001834 sdram_ddr1 = true;
Stefan Roese43f32472007-02-20 10:43:34 +01001835
1836 /* loop through all the DIMM slots on the board */
1837 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1838 /* If a dimm is installed in a particular slot ... */
1839 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1840 if (dimm_populated[dimm_num] == SDRAM_DDR2)
York Sun4a598092013-04-01 11:29:11 -07001841 sdram_ddr1 = true;
Stefan Roese43f32472007-02-20 10:43:34 +01001842 else
York Sun4a598092013-04-01 11:29:11 -07001843 sdram_ddr1 = false;
Stefan Roese43f32472007-02-20 10:43:34 +01001844
1845 t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1846 t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1847 t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1848 t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1849 t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
1850 t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1851 }
1852 }
1853
1854 /*------------------------------------------------------------------
1855 * Set the SDRAM Timing Reg 1, SDRAM_TR1
1856 *-----------------------------------------------------------------*/
1857 mfsdram(SDRAM_SDTR1, sdtr1);
1858 sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1859 SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1860
1861 /* default values */
1862 sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1863 sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1864
1865 /* normal operations */
1866 sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1867 sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1868
1869 mtsdram(SDRAM_SDTR1, sdtr1);
1870
1871 /*------------------------------------------------------------------
1872 * Set the SDRAM Timing Reg 2, SDRAM_TR2
1873 *-----------------------------------------------------------------*/
1874 mfsdram(SDRAM_SDTR2, sdtr2);
1875 sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK |
1876 SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1877 SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK |
1878 SDRAM_SDTR2_RRD_MASK);
1879
1880 /*
1881 * convert t_rcd from nanoseconds to ddr clocks
1882 * round up if necessary
1883 */
1884 t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1885 ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1886 if (sdram_freq != ddr_check)
1887 t_rcd_clk++;
1888
1889 switch (t_rcd_clk) {
1890 case 0:
1891 case 1:
1892 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1893 break;
1894 case 2:
1895 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1896 break;
1897 case 3:
1898 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1899 break;
1900 case 4:
1901 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1902 break;
1903 default:
1904 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1905 break;
1906 }
1907
York Sun4a598092013-04-01 11:29:11 -07001908 if (sdram_ddr1 == true) { /* DDR1 */
Stefan Roese43f32472007-02-20 10:43:34 +01001909 if (sdram_freq < 200000000) {
1910 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1911 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1912 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1913 } else {
1914 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1915 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1916 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1917 }
1918 } else { /* DDR2 */
1919 /* loop through all the DIMM slots on the board */
1920 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1921 /* If a dimm is installed in a particular slot ... */
1922 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1923 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1924 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1925 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1926 }
1927 }
1928
1929 /*
1930 * convert from nanoseconds to ddr clocks
1931 * round up if necessary
1932 */
1933 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1934 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1935 if (sdram_freq != ddr_check)
1936 t_wpc_clk++;
1937
1938 switch (t_wpc_clk) {
1939 case 0:
1940 case 1:
1941 case 2:
1942 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1943 break;
1944 case 3:
1945 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1946 break;
1947 case 4:
1948 sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1949 break;
1950 case 5:
1951 sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1952 break;
1953 default:
1954 sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1955 break;
1956 }
1957
1958 /*
1959 * convert from nanoseconds to ddr clocks
1960 * round up if necessary
1961 */
1962 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1963 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1964 if (sdram_freq != ddr_check)
1965 t_wtr_clk++;
1966
1967 switch (t_wtr_clk) {
1968 case 0:
1969 case 1:
1970 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1971 break;
1972 case 2:
1973 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1974 break;
1975 case 3:
1976 sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1977 break;
1978 default:
1979 sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1980 break;
1981 }
1982
1983 /*
1984 * convert from nanoseconds to ddr clocks
1985 * round up if necessary
1986 */
1987 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1988 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1989 if (sdram_freq != ddr_check)
1990 t_rpc_clk++;
1991
1992 switch (t_rpc_clk) {
1993 case 0:
1994 case 1:
1995 case 2:
1996 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1997 break;
1998 case 3:
1999 sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
2000 break;
2001 default:
2002 sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
2003 break;
2004 }
2005 }
2006
2007 /* default value */
2008 sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
2009
2010 /*
2011 * convert t_rrd from nanoseconds to ddr clocks
2012 * round up if necessary
2013 */
2014 t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
2015 ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
2016 if (sdram_freq != ddr_check)
2017 t_rrd_clk++;
2018
2019 if (t_rrd_clk == 3)
2020 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
2021 else
2022 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
2023
2024 /*
2025 * convert t_rp from nanoseconds to ddr clocks
2026 * round up if necessary
2027 */
2028 t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
2029 ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
2030 if (sdram_freq != ddr_check)
2031 t_rp_clk++;
2032
2033 switch (t_rp_clk) {
2034 case 0:
2035 case 1:
2036 case 2:
2037 case 3:
2038 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2039 break;
2040 case 4:
2041 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2042 break;
2043 case 5:
2044 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2045 break;
2046 case 6:
2047 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2048 break;
2049 default:
2050 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2051 break;
2052 }
2053
2054 mtsdram(SDRAM_SDTR2, sdtr2);
2055
2056 /*------------------------------------------------------------------
2057 * Set the SDRAM Timing Reg 3, SDRAM_TR3
2058 *-----------------------------------------------------------------*/
2059 mfsdram(SDRAM_SDTR3, sdtr3);
2060 sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK |
2061 SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2062
2063 /*
2064 * convert t_ras from nanoseconds to ddr clocks
2065 * round up if necessary
2066 */
2067 t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2068 ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2069 if (sdram_freq != ddr_check)
2070 t_ras_clk++;
2071
2072 sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2073
2074 /*
2075 * convert t_rc from nanoseconds to ddr clocks
2076 * round up if necessary
2077 */
2078 t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2079 ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2080 if (sdram_freq != ddr_check)
2081 t_rc_clk++;
2082
2083 sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2084
2085 /* default xcs value */
2086 sdtr3 |= SDRAM_SDTR3_XCS;
2087
2088 /*
2089 * convert t_rfc from nanoseconds to ddr clocks
2090 * round up if necessary
2091 */
2092 t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2093 ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2094 if (sdram_freq != ddr_check)
2095 t_rfc_clk++;
2096
2097 sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2098
2099 mtsdram(SDRAM_SDTR3, sdtr3);
2100}
2101
2102/*-----------------------------------------------------------------------------+
2103 * program_bxcf.
2104 *-----------------------------------------------------------------------------*/
2105static void program_bxcf(unsigned long *dimm_populated,
2106 unsigned char *iic0_dimm_addr,
2107 unsigned long num_dimm_banks)
2108{
2109 unsigned long dimm_num;
2110 unsigned long num_col_addr;
2111 unsigned long num_ranks;
2112 unsigned long num_banks;
2113 unsigned long mode;
2114 unsigned long ind_rank;
2115 unsigned long ind;
2116 unsigned long ind_bank;
2117 unsigned long bank_0_populated;
2118
2119 /*------------------------------------------------------------------
2120 * Set the BxCF regs. First, wipe out the bank config registers.
2121 *-----------------------------------------------------------------*/
Stefan Roeseedd73f22007-10-21 08:12:41 +02002122 mtsdram(SDRAM_MB0CF, 0x00000000);
2123 mtsdram(SDRAM_MB1CF, 0x00000000);
2124 mtsdram(SDRAM_MB2CF, 0x00000000);
2125 mtsdram(SDRAM_MB3CF, 0x00000000);
Stefan Roese43f32472007-02-20 10:43:34 +01002126
2127 mode = SDRAM_BXCF_M_BE_ENABLE;
2128
2129 bank_0_populated = 0;
2130
2131 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2132 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2133 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2134 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2135 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2136 num_ranks = (num_ranks & 0x0F) +1;
2137 else
2138 num_ranks = num_ranks & 0x0F;
2139
2140 num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2141
2142 for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2143 if (num_banks == 4)
2144 ind = 0;
2145 else
Stefan Roese964754e2008-04-30 10:49:43 +02002146 ind = 5 << 8;
Stefan Roese43f32472007-02-20 10:43:34 +01002147 switch (num_col_addr) {
2148 case 0x08:
2149 mode |= (SDRAM_BXCF_M_AM_0 + ind);
2150 break;
2151 case 0x09:
2152 mode |= (SDRAM_BXCF_M_AM_1 + ind);
2153 break;
2154 case 0x0A:
2155 mode |= (SDRAM_BXCF_M_AM_2 + ind);
2156 break;
2157 case 0x0B:
2158 mode |= (SDRAM_BXCF_M_AM_3 + ind);
2159 break;
2160 case 0x0C:
2161 mode |= (SDRAM_BXCF_M_AM_4 + ind);
2162 break;
2163 default:
2164 printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2165 (unsigned int)dimm_num);
2166 printf("ERROR: Unsupported value for number of "
2167 "column addresses: %d.\n", (unsigned int)num_col_addr);
2168 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schocher68310b02007-06-25 19:11:37 +02002169 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +01002170 }
2171 }
2172
2173 if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2174 bank_0_populated = 1;
2175
2176 for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
Stefan Roeseedd73f22007-10-21 08:12:41 +02002177 mtsdram(SDRAM_MB0CF +
2178 ((dimm_num + bank_0_populated + ind_rank) << 2),
2179 mode);
Stefan Roese43f32472007-02-20 10:43:34 +01002180 }
2181 }
2182 }
2183}
2184
2185/*------------------------------------------------------------------
2186 * program memory queue.
2187 *-----------------------------------------------------------------*/
2188static void program_memory_queue(unsigned long *dimm_populated,
2189 unsigned char *iic0_dimm_addr,
2190 unsigned long num_dimm_banks)
2191{
2192 unsigned long dimm_num;
Stefan Roese0203a972008-07-09 17:33:57 +02002193 phys_size_t rank_base_addr;
Stefan Roese43f32472007-02-20 10:43:34 +01002194 unsigned long rank_reg;
Stefan Roese0203a972008-07-09 17:33:57 +02002195 phys_size_t rank_size_bytes;
Stefan Roese43f32472007-02-20 10:43:34 +01002196 unsigned long rank_size_id;
2197 unsigned long num_ranks;
2198 unsigned long baseadd_size;
2199 unsigned long i;
2200 unsigned long bank_0_populated = 0;
Stefan Roese0203a972008-07-09 17:33:57 +02002201 phys_size_t total_size = 0;
Stefan Roese43f32472007-02-20 10:43:34 +01002202
2203 /*------------------------------------------------------------------
2204 * Reset the rank_base_address.
2205 *-----------------------------------------------------------------*/
2206 rank_reg = SDRAM_R0BAS;
2207
2208 rank_base_addr = 0x00000000;
2209
2210 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2211 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2212 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2213 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2214 num_ranks = (num_ranks & 0x0F) + 1;
2215 else
2216 num_ranks = num_ranks & 0x0F;
2217
2218 rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2219
2220 /*------------------------------------------------------------------
2221 * Set the sizes
2222 *-----------------------------------------------------------------*/
2223 baseadd_size = 0;
Stefan Roese43f32472007-02-20 10:43:34 +01002224 switch (rank_size_id) {
Stefan Roesebdd13d12008-03-11 15:05:26 +01002225 case 0x01:
2226 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2227 total_size = 1024;
2228 break;
Stefan Roese43f32472007-02-20 10:43:34 +01002229 case 0x02:
Stefan Roesebdd13d12008-03-11 15:05:26 +01002230 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2231 total_size = 2048;
Stefan Roese43f32472007-02-20 10:43:34 +01002232 break;
2233 case 0x04:
Stefan Roesebdd13d12008-03-11 15:05:26 +01002234 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2235 total_size = 4096;
Stefan Roese43f32472007-02-20 10:43:34 +01002236 break;
2237 case 0x08:
2238 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
Stefan Roesebdd13d12008-03-11 15:05:26 +01002239 total_size = 32;
Stefan Roese43f32472007-02-20 10:43:34 +01002240 break;
2241 case 0x10:
2242 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
Stefan Roesebdd13d12008-03-11 15:05:26 +01002243 total_size = 64;
Stefan Roese43f32472007-02-20 10:43:34 +01002244 break;
2245 case 0x20:
2246 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
Stefan Roesebdd13d12008-03-11 15:05:26 +01002247 total_size = 128;
Stefan Roese43f32472007-02-20 10:43:34 +01002248 break;
2249 case 0x40:
2250 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
Stefan Roesebdd13d12008-03-11 15:05:26 +01002251 total_size = 256;
Stefan Roese43f32472007-02-20 10:43:34 +01002252 break;
2253 case 0x80:
2254 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
Stefan Roesebdd13d12008-03-11 15:05:26 +01002255 total_size = 512;
Stefan Roese43f32472007-02-20 10:43:34 +01002256 break;
2257 default:
2258 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2259 (unsigned int)dimm_num);
2260 printf("ERROR: Unsupported value for the banksize: %d.\n",
2261 (unsigned int)rank_size_id);
2262 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schocher68310b02007-06-25 19:11:37 +02002263 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +01002264 }
Stefan Roesebdd13d12008-03-11 15:05:26 +01002265 rank_size_bytes = total_size << 20;
Stefan Roese43f32472007-02-20 10:43:34 +01002266
2267 if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2268 bank_0_populated = 1;
2269
2270 for (i = 0; i < num_ranks; i++) {
2271 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
Stefan Roeseb39ef632007-03-08 10:06:09 +01002272 (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2273 baseadd_size));
Stefan Roese43f32472007-02-20 10:43:34 +01002274 rank_base_addr += rank_size_bytes;
2275 }
2276 }
2277 }
Stefan Roesebdd13d12008-03-11 15:05:26 +01002278
Prodyut Hazarika038f0d82008-08-20 09:38:51 -07002279#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2280 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2281 defined(CONFIG_460SX)
Stefan Roesebdd13d12008-03-11 15:05:26 +01002282 /*
Prodyut Hazarika038f0d82008-08-20 09:38:51 -07002283 * Enable high bandwidth access
Stefan Roesebdd13d12008-03-11 15:05:26 +01002284 * This is currently not used, but with this setup
2285 * it is possible to use it later on in e.g. the Linux
2286 * EMAC driver for performance gain.
2287 */
2288 mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2289 mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
Prodyut Hazarika038f0d82008-08-20 09:38:51 -07002290
2291 /*
2292 * Set optimal value for Memory Queue HB/LL Configuration registers
2293 */
Yuri Tikhonovbbfab702008-10-17 12:54:18 +02002294 mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
2295 SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
2296 SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
2297 mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
2298 SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
2299 SDRAM_CONF1LL_RPLM);
Stefan Roese1abbbd02008-08-21 11:05:03 +02002300 mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
Stefan Roesebdd13d12008-03-11 15:05:26 +01002301#endif
Stefan Roese43f32472007-02-20 10:43:34 +01002302}
2303
Stefan Roeseb39ef632007-03-08 10:06:09 +01002304#ifdef CONFIG_DDR_ECC
Stefan Roese43f32472007-02-20 10:43:34 +01002305/*-----------------------------------------------------------------------------+
2306 * program_ecc.
2307 *-----------------------------------------------------------------------------*/
2308static void program_ecc(unsigned long *dimm_populated,
2309 unsigned char *iic0_dimm_addr,
Stefan Roesebad41112007-03-01 21:11:36 +01002310 unsigned long num_dimm_banks,
2311 unsigned long tlb_word2_i_value)
Stefan Roese43f32472007-02-20 10:43:34 +01002312{
Stefan Roese43f32472007-02-20 10:43:34 +01002313 unsigned long dimm_num;
2314 unsigned long ecc;
2315
2316 ecc = 0;
2317 /* loop through all the DIMM slots on the board */
2318 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2319 /* If a dimm is installed in a particular slot ... */
2320 if (dimm_populated[dimm_num] != SDRAM_NONE)
2321 ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2322 }
2323 if (ecc == 0)
2324 return;
Stefan Roesebad41112007-03-01 21:11:36 +01002325
Felix Radensky0e925362009-09-27 23:56:12 +02002326 do_program_ecc(tlb_word2_i_value);
Stefan Roese43f32472007-02-20 10:43:34 +01002327}
Stefan Roeseb39ef632007-03-08 10:06:09 +01002328#endif
Stefan Roese43f32472007-02-20 10:43:34 +01002329
Adam Graham97a55812008-09-03 12:26:59 -07002330#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
Stefan Roese43f32472007-02-20 10:43:34 +01002331/*-----------------------------------------------------------------------------+
2332 * program_DQS_calibration.
2333 *-----------------------------------------------------------------------------*/
2334static void program_DQS_calibration(unsigned long *dimm_populated,
2335 unsigned char *iic0_dimm_addr,
2336 unsigned long num_dimm_banks)
2337{
2338 unsigned long val;
2339
2340#ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2341 mtsdram(SDRAM_RQDC, 0x80000037);
2342 mtsdram(SDRAM_RDCC, 0x40000000);
2343 mtsdram(SDRAM_RFDC, 0x000001DF);
2344
2345 test();
2346#else
2347 /*------------------------------------------------------------------
2348 * Program RDCC register
2349 * Read sample cycle auto-update enable
2350 *-----------------------------------------------------------------*/
2351
Stefan Roese43f32472007-02-20 10:43:34 +01002352 mfsdram(SDRAM_RDCC, val);
2353 mtsdram(SDRAM_RDCC,
2354 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
Stefan Roesee3060b02008-01-05 09:12:41 +01002355 | SDRAM_RDCC_RSAE_ENABLE);
Stefan Roese43f32472007-02-20 10:43:34 +01002356
2357 /*------------------------------------------------------------------
2358 * Program RQDC register
2359 * Internal DQS delay mechanism enable
2360 *-----------------------------------------------------------------*/
2361 mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2362
2363 /*------------------------------------------------------------------
2364 * Program RFDC register
2365 * Set Feedback Fractional Oversample
2366 * Auto-detect read sample cycle enable
Prodyut Hazarika52b6bec2008-08-27 16:39:00 -07002367 * Set RFOS to 1/4 of memclk cycle (0x3f)
Stefan Roese43f32472007-02-20 10:43:34 +01002368 *-----------------------------------------------------------------*/
2369 mfsdram(SDRAM_RFDC, val);
2370 mtsdram(SDRAM_RFDC,
2371 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2372 SDRAM_RFDC_RFFD_MASK))
Prodyut Hazarika52b6bec2008-08-27 16:39:00 -07002373 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
Stefan Roese43f32472007-02-20 10:43:34 +01002374 SDRAM_RFDC_RFFD_ENCODE(0)));
2375
2376 DQS_calibration_process();
2377#endif
2378}
2379
Stefan Roesef88e3602007-03-31 08:46:08 +02002380static int short_mem_test(void)
Stefan Roese43f32472007-02-20 10:43:34 +01002381{
2382 u32 *membase;
2383 u32 bxcr_num;
2384 u32 bxcf;
2385 int i;
2386 int j;
Stefan Roese0203a972008-07-09 17:33:57 +02002387 phys_size_t base_addr;
Stefan Roese43f32472007-02-20 10:43:34 +01002388 u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2389 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2390 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2391 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2392 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2393 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2394 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2395 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2396 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2397 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2398 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2399 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2400 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2401 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2402 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2403 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2404 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
Stefan Roesef88e3602007-03-31 08:46:08 +02002405 int l;
Stefan Roese43f32472007-02-20 10:43:34 +01002406
2407 for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2408 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2409
2410 /* Banks enabled */
2411 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
Stefan Roese43f32472007-02-20 10:43:34 +01002412 /* Bank is enabled */
Stefan Roese43f32472007-02-20 10:43:34 +01002413
Stefan Roese0203a972008-07-09 17:33:57 +02002414 /*
2415 * Only run test on accessable memory (below 2GB)
2416 */
2417 base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2418 if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2419 continue;
2420
Stefan Roese43f32472007-02-20 10:43:34 +01002421 /*------------------------------------------------------------------
2422 * Run the short memory test.
2423 *-----------------------------------------------------------------*/
Stefan Roese0203a972008-07-09 17:33:57 +02002424 membase = (u32 *)(u32)base_addr;
Stefan Roesef88e3602007-03-31 08:46:08 +02002425
Stefan Roese43f32472007-02-20 10:43:34 +01002426 for (i = 0; i < NUMMEMTESTS; i++) {
2427 for (j = 0; j < NUMMEMWORDS; j++) {
2428 membase[j] = test[i][j];
2429 ppcDcbf((u32)&(membase[j]));
2430 }
2431 sync();
Stefan Roesef88e3602007-03-31 08:46:08 +02002432 for (l=0; l<NUMLOOPS; l++) {
2433 for (j = 0; j < NUMMEMWORDS; j++) {
2434 if (membase[j] != test[i][j]) {
2435 ppcDcbf((u32)&(membase[j]));
2436 return 0;
2437 }
Stefan Roese43f32472007-02-20 10:43:34 +01002438 ppcDcbf((u32)&(membase[j]));
Stefan Roese43f32472007-02-20 10:43:34 +01002439 }
Stefan Roesef88e3602007-03-31 08:46:08 +02002440 sync();
Stefan Roese43f32472007-02-20 10:43:34 +01002441 }
Stefan Roese43f32472007-02-20 10:43:34 +01002442 }
Stefan Roese43f32472007-02-20 10:43:34 +01002443 } /* if bank enabled */
2444 } /* for bxcf_num */
2445
Stefan Roesef88e3602007-03-31 08:46:08 +02002446 return 1;
Stefan Roese43f32472007-02-20 10:43:34 +01002447}
2448
2449#ifndef HARD_CODED_DQS
2450/*-----------------------------------------------------------------------------+
2451 * DQS_calibration_process.
2452 *-----------------------------------------------------------------------------*/
2453static void DQS_calibration_process(void)
2454{
Stefan Roese43f32472007-02-20 10:43:34 +01002455 unsigned long rfdc_reg;
2456 unsigned long rffd;
Stefan Roese43f32472007-02-20 10:43:34 +01002457 unsigned long val;
Stefan Roese43f32472007-02-20 10:43:34 +01002458 long rffd_average;
2459 long max_start;
Stefan Roese43f32472007-02-20 10:43:34 +01002460 unsigned long dlycal;
2461 unsigned long dly_val;
2462 unsigned long max_pass_length;
2463 unsigned long current_pass_length;
2464 unsigned long current_fail_length;
2465 unsigned long current_start;
2466 long max_end;
2467 unsigned char fail_found;
2468 unsigned char pass_found;
Stefan Roesee3060b02008-01-05 09:12:41 +01002469#if !defined(CONFIG_DDR_RQDC_FIXED)
Stefan Roese65a57122011-11-15 08:02:30 +00002470 int window_found;
Stefan Roesee3060b02008-01-05 09:12:41 +01002471 u32 rqdc_reg;
2472 u32 rqfd;
Stefan Roesef88e3602007-03-31 08:46:08 +02002473 u32 rqfd_start;
Stefan Roesee3060b02008-01-05 09:12:41 +01002474 u32 rqfd_average;
2475 int loopi = 0;
Stefan Roesef88e3602007-03-31 08:46:08 +02002476 char str[] = "Auto calibration -";
2477 char slash[] = "\\|/-\\|/-";
Stefan Roese43f32472007-02-20 10:43:34 +01002478
2479 /*------------------------------------------------------------------
2480 * Test to determine the best read clock delay tuning bits.
2481 *
2482 * Before the DDR controller can be used, the read clock delay needs to be
2483 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2484 * This value cannot be hardcoded into the program because it changes
2485 * depending on the board's setup and environment.
2486 * To do this, all delay values are tested to see if they
2487 * work or not. By doing this, you get groups of fails with groups of
2488 * passing values. The idea is to find the start and end of a passing
2489 * window and take the center of it to use as the read clock delay.
2490 *
2491 * A failure has to be seen first so that when we hit a pass, we know
2492 * that it is truely the start of the window. If we get passing values
2493 * to start off with, we don't know if we are at the start of the window.
2494 *
2495 * The code assumes that a failure will always be found.
2496 * If a failure is not found, there is no easy way to get the middle
2497 * of the passing window. I guess we can pretty much pick any value
2498 * but some values will be better than others. Since the lowest speed
2499 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2500 * from experimentation it is safe to say you will always have a failure.
2501 *-----------------------------------------------------------------*/
Stefan Roesef88e3602007-03-31 08:46:08 +02002502
2503 /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2504 rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2505
2506 puts(str);
2507
2508calibration_loop:
2509 mfsdram(SDRAM_RQDC, rqdc_reg);
2510 mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2511 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
Stefan Roesee3060b02008-01-05 09:12:41 +01002512#else /* CONFIG_DDR_RQDC_FIXED */
2513 /*
2514 * On Katmai the complete auto-calibration somehow doesn't seem to
2515 * produce the best results, meaning optimal values for RQFD/RFFD.
2516 * This was discovered by GDA using a high bandwidth scope,
2517 * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2518 * so now on Katmai "only" RFFD is auto-calibrated.
2519 */
2520 mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2521#endif /* CONFIG_DDR_RQDC_FIXED */
Stefan Roese43f32472007-02-20 10:43:34 +01002522
2523 max_start = 0;
Stefan Roese43f32472007-02-20 10:43:34 +01002524
2525 max_pass_length = 0;
2526 max_start = 0;
2527 max_end = 0;
2528 current_pass_length = 0;
2529 current_fail_length = 0;
2530 current_start = 0;
York Sun4a598092013-04-01 11:29:11 -07002531 fail_found = false;
2532 pass_found = false;
Stefan Roese43f32472007-02-20 10:43:34 +01002533
Stefan Roese43f32472007-02-20 10:43:34 +01002534 /*
2535 * get the delay line calibration register value
2536 */
2537 mfsdram(SDRAM_DLCR, dlycal);
2538 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2539
2540 for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2541 mfsdram(SDRAM_RFDC, rfdc_reg);
2542 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2543
2544 /*------------------------------------------------------------------
2545 * Set the timing reg for the test.
2546 *-----------------------------------------------------------------*/
2547 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2548
Stefan Roese43f32472007-02-20 10:43:34 +01002549 /*------------------------------------------------------------------
2550 * See if the rffd value passed.
2551 *-----------------------------------------------------------------*/
Stefan Roesef88e3602007-03-31 08:46:08 +02002552 if (short_mem_test()) {
York Sun4a598092013-04-01 11:29:11 -07002553 if (fail_found == true) {
2554 pass_found = true;
Stefan Roese43f32472007-02-20 10:43:34 +01002555 if (current_pass_length == 0)
2556 current_start = rffd;
2557
2558 current_fail_length = 0;
2559 current_pass_length++;
2560
2561 if (current_pass_length > max_pass_length) {
2562 max_pass_length = current_pass_length;
2563 max_start = current_start;
2564 max_end = rffd;
2565 }
2566 }
2567 } else {
2568 current_pass_length = 0;
2569 current_fail_length++;
2570
2571 if (current_fail_length >= (dly_val >> 2)) {
York Sun4a598092013-04-01 11:29:11 -07002572 if (fail_found == false)
2573 fail_found = true;
2574 else if (pass_found == true)
Stefan Roese43f32472007-02-20 10:43:34 +01002575 break;
Stefan Roese43f32472007-02-20 10:43:34 +01002576 }
2577 }
2578 } /* for rffd */
2579
Stefan Roese43f32472007-02-20 10:43:34 +01002580 /*------------------------------------------------------------------
2581 * Set the average RFFD value
2582 *-----------------------------------------------------------------*/
2583 rffd_average = ((max_start + max_end) >> 1);
2584
2585 if (rffd_average < 0)
2586 rffd_average = 0;
2587
2588 if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2589 rffd_average = SDRAM_RFDC_RFFD_MAX;
2590 /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2591 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2592
Stefan Roesee3060b02008-01-05 09:12:41 +01002593#if !defined(CONFIG_DDR_RQDC_FIXED)
Stefan Roese43f32472007-02-20 10:43:34 +01002594 max_pass_length = 0;
2595 max_start = 0;
2596 max_end = 0;
2597 current_pass_length = 0;
2598 current_fail_length = 0;
2599 current_start = 0;
York Sun4a598092013-04-01 11:29:11 -07002600 window_found = false;
2601 fail_found = false;
2602 pass_found = false;
Stefan Roese43f32472007-02-20 10:43:34 +01002603
2604 for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2605 mfsdram(SDRAM_RQDC, rqdc_reg);
2606 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2607
2608 /*------------------------------------------------------------------
2609 * Set the timing reg for the test.
2610 *-----------------------------------------------------------------*/
2611 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2612
Stefan Roese43f32472007-02-20 10:43:34 +01002613 /*------------------------------------------------------------------
2614 * See if the rffd value passed.
2615 *-----------------------------------------------------------------*/
Stefan Roesef88e3602007-03-31 08:46:08 +02002616 if (short_mem_test()) {
York Sun4a598092013-04-01 11:29:11 -07002617 if (fail_found == true) {
2618 pass_found = true;
Stefan Roese43f32472007-02-20 10:43:34 +01002619 if (current_pass_length == 0)
2620 current_start = rqfd;
2621
2622 current_fail_length = 0;
2623 current_pass_length++;
2624
2625 if (current_pass_length > max_pass_length) {
2626 max_pass_length = current_pass_length;
2627 max_start = current_start;
2628 max_end = rqfd;
2629 }
2630 }
2631 } else {
2632 current_pass_length = 0;
2633 current_fail_length++;
2634
York Sun4a598092013-04-01 11:29:11 -07002635 if (fail_found == false) {
2636 fail_found = true;
2637 } else if (pass_found == true) {
2638 window_found = true;
Stefan Roese43f32472007-02-20 10:43:34 +01002639 break;
2640 }
2641 }
2642 }
2643
Stefan Roesef88e3602007-03-31 08:46:08 +02002644 rqfd_average = ((max_start + max_end) >> 1);
2645
Stefan Roese43f32472007-02-20 10:43:34 +01002646 /*------------------------------------------------------------------
2647 * Make sure we found the valid read passing window. Halt if not
2648 *-----------------------------------------------------------------*/
York Sun4a598092013-04-01 11:29:11 -07002649 if (window_found == false) {
Stefan Roesef88e3602007-03-31 08:46:08 +02002650 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2651 putc('\b');
2652 putc(slash[loopi++ % 8]);
2653
2654 /* try again from with a different RQFD start value */
2655 rqfd_start++;
2656 goto calibration_loop;
2657 }
2658
2659 printf("\nERROR: Cannot determine a common read delay for the "
Stefan Roese43f32472007-02-20 10:43:34 +01002660 "DIMM(s) installed.\n");
2661 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
Grant Erickson9416cd92008-07-09 16:46:35 -07002662 ppc4xx_ibm_ddr2_register_dump();
Heiko Schocher68310b02007-06-25 19:11:37 +02002663 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +01002664 }
2665
Stefan Roese43f32472007-02-20 10:43:34 +01002666 if (rqfd_average < 0)
2667 rqfd_average = 0;
2668
2669 if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2670 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2671
Stefan Roese43f32472007-02-20 10:43:34 +01002672 mtsdram(SDRAM_RQDC,
2673 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2674 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2675
Stefan Roesee3060b02008-01-05 09:12:41 +01002676 blank_string(strlen(str));
2677#endif /* CONFIG_DDR_RQDC_FIXED */
2678
Stefan Roese43f32472007-02-20 10:43:34 +01002679 mfsdram(SDRAM_DLCR, val);
Felix Radensky8d4d4a62009-07-01 11:37:46 +03002680 debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val);
Stefan Roese43f32472007-02-20 10:43:34 +01002681 mfsdram(SDRAM_RQDC, val);
Felix Radensky8d4d4a62009-07-01 11:37:46 +03002682 debug("%s[%d] RQDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
Stefan Roese43f32472007-02-20 10:43:34 +01002683 mfsdram(SDRAM_RFDC, val);
Felix Radensky8d4d4a62009-07-01 11:37:46 +03002684 debug("%s[%d] RFDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
Stefan Roesee3060b02008-01-05 09:12:41 +01002685 mfsdram(SDRAM_RDCC, val);
Felix Radensky8d4d4a62009-07-01 11:37:46 +03002686 debug("%s[%d] RDCC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
Stefan Roese43f32472007-02-20 10:43:34 +01002687}
2688#else /* calibration test with hardvalues */
2689/*-----------------------------------------------------------------------------+
2690 * DQS_calibration_process.
2691 *-----------------------------------------------------------------------------*/
2692static void test(void)
2693{
2694 unsigned long dimm_num;
2695 unsigned long ecc_temp;
2696 unsigned long i, j;
2697 unsigned long *membase;
2698 unsigned long bxcf[MAXRANKS];
2699 unsigned long val;
2700 char window_found;
2701 char begin_found[MAXDIMMS];
2702 char end_found[MAXDIMMS];
2703 char search_end[MAXDIMMS];
2704 unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2705 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2706 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2707 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2708 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2709 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2710 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2711 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2712 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2713 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2714 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2715 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2716 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2717 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2718 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2719 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2720 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2721
2722 /*------------------------------------------------------------------
2723 * Test to determine the best read clock delay tuning bits.
2724 *
2725 * Before the DDR controller can be used, the read clock delay needs to be
2726 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2727 * This value cannot be hardcoded into the program because it changes
2728 * depending on the board's setup and environment.
2729 * To do this, all delay values are tested to see if they
2730 * work or not. By doing this, you get groups of fails with groups of
2731 * passing values. The idea is to find the start and end of a passing
2732 * window and take the center of it to use as the read clock delay.
2733 *
2734 * A failure has to be seen first so that when we hit a pass, we know
2735 * that it is truely the start of the window. If we get passing values
2736 * to start off with, we don't know if we are at the start of the window.
2737 *
2738 * The code assumes that a failure will always be found.
2739 * If a failure is not found, there is no easy way to get the middle
2740 * of the passing window. I guess we can pretty much pick any value
2741 * but some values will be better than others. Since the lowest speed
2742 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2743 * from experimentation it is safe to say you will always have a failure.
2744 *-----------------------------------------------------------------*/
2745 mfsdram(SDRAM_MCOPT1, ecc_temp);
2746 ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2747 mfsdram(SDRAM_MCOPT1, val);
2748 mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2749 SDRAM_MCOPT1_MCHK_NON);
2750
York Sun4a598092013-04-01 11:29:11 -07002751 window_found = false;
2752 begin_found[0] = false;
2753 end_found[0] = false;
2754 search_end[0] = false;
2755 begin_found[1] = false;
2756 end_found[1] = false;
2757 search_end[1] = false;
Stefan Roese43f32472007-02-20 10:43:34 +01002758
2759 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2760 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2761
2762 /* Banks enabled */
2763 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2764
2765 /* Bank is enabled */
2766 membase =
2767 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2768
2769 /*------------------------------------------------------------------
2770 * Run the short memory test.
2771 *-----------------------------------------------------------------*/
2772 for (i = 0; i < NUMMEMTESTS; i++) {
2773 for (j = 0; j < NUMMEMWORDS; j++) {
2774 membase[j] = test[i][j];
2775 ppcDcbf((u32)&(membase[j]));
2776 }
2777 sync();
2778 for (j = 0; j < NUMMEMWORDS; j++) {
2779 if (membase[j] != test[i][j]) {
2780 ppcDcbf((u32)&(membase[j]));
2781 break;
2782 }
2783 ppcDcbf((u32)&(membase[j]));
2784 }
2785 sync();
2786 if (j < NUMMEMWORDS)
2787 break;
2788 }
2789
2790 /*------------------------------------------------------------------
2791 * See if the rffd value passed.
2792 *-----------------------------------------------------------------*/
2793 if (i < NUMMEMTESTS) {
York Sun4a598092013-04-01 11:29:11 -07002794 if ((end_found[dimm_num] == false) &&
2795 (search_end[dimm_num] == true)) {
2796 end_found[dimm_num] = true;
Stefan Roese43f32472007-02-20 10:43:34 +01002797 }
York Sun4a598092013-04-01 11:29:11 -07002798 if ((end_found[0] == true) &&
2799 (end_found[1] == true))
Stefan Roese43f32472007-02-20 10:43:34 +01002800 break;
2801 } else {
York Sun4a598092013-04-01 11:29:11 -07002802 if (begin_found[dimm_num] == false) {
2803 begin_found[dimm_num] = true;
2804 search_end[dimm_num] = true;
Stefan Roese43f32472007-02-20 10:43:34 +01002805 }
2806 }
2807 } else {
York Sun4a598092013-04-01 11:29:11 -07002808 begin_found[dimm_num] = true;
2809 end_found[dimm_num] = true;
Stefan Roese43f32472007-02-20 10:43:34 +01002810 }
2811 }
2812
York Sun4a598092013-04-01 11:29:11 -07002813 if ((begin_found[0] == true) && (begin_found[1] == true))
2814 window_found = true;
Stefan Roese43f32472007-02-20 10:43:34 +01002815
2816 /*------------------------------------------------------------------
2817 * Make sure we found the valid read passing window. Halt if not
2818 *-----------------------------------------------------------------*/
York Sun4a598092013-04-01 11:29:11 -07002819 if (window_found == false) {
Stefan Roese43f32472007-02-20 10:43:34 +01002820 printf("ERROR: Cannot determine a common read delay for the "
2821 "DIMM(s) installed.\n");
Heiko Schocher68310b02007-06-25 19:11:37 +02002822 spd_ddr_init_hang ();
Stefan Roese43f32472007-02-20 10:43:34 +01002823 }
2824
2825 /*------------------------------------------------------------------
2826 * Restore the ECC variable to what it originally was
2827 *-----------------------------------------------------------------*/
2828 mtsdram(SDRAM_MCOPT1,
2829 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2830 | ecc_temp);
2831}
Adam Graham97a55812008-09-03 12:26:59 -07002832#endif /* !HARD_CODED_DQS */
2833#endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
Stefan Roese43f32472007-02-20 10:43:34 +01002834
Stefan Roese2001a332008-07-10 15:32:32 +02002835#else /* CONFIG_SPD_EEPROM */
2836
Grant Ericksonb6933412008-05-22 14:44:14 -07002837/*-----------------------------------------------------------------------------
2838 * Function: initdram
Adam Graham446eb8d2008-10-08 10:13:14 -07002839 * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
2840 * The configuration is performed using static, compile-
Grant Ericksonb6933412008-05-22 14:44:14 -07002841 * time parameters.
Adam Graham446eb8d2008-10-08 10:13:14 -07002842 * Configures the PPC405EX(r) and PPC460EX/GT
Grant Ericksonb6933412008-05-22 14:44:14 -07002843 *---------------------------------------------------------------------------*/
Becky Brucebd99ae72008-06-09 16:03:40 -05002844phys_size_t initdram(int board_type)
Grant Ericksonb6933412008-05-22 14:44:14 -07002845{
Stefan Roesea226c852008-06-02 17:13:55 +02002846 /*
2847 * Only run this SDRAM init code once. For NAND booting
2848 * targets like Kilauea, we call initdram() early from the
2849 * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
2850 * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
2851 * which calls initdram() again. This time the controller
2852 * mustn't be reconfigured again since we're already running
2853 * from SDRAM.
2854 */
2855#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
Grant Ericksonb6933412008-05-22 14:44:14 -07002856 unsigned long val;
2857
Adam Graham446eb8d2008-10-08 10:13:14 -07002858#if defined(CONFIG_440)
2859 mtdcr(SDRAM_R0BAS, CONFIG_SYS_SDRAM_R0BAS);
2860 mtdcr(SDRAM_R1BAS, CONFIG_SYS_SDRAM_R1BAS);
2861 mtdcr(SDRAM_R2BAS, CONFIG_SYS_SDRAM_R2BAS);
2862 mtdcr(SDRAM_R3BAS, CONFIG_SYS_SDRAM_R3BAS);
2863 mtdcr(SDRAM_PLBADDULL, CONFIG_SYS_SDRAM_PLBADDULL); /* MQ0_BAUL */
2864 mtdcr(SDRAM_PLBADDUHB, CONFIG_SYS_SDRAM_PLBADDUHB); /* MQ0_BAUH */
2865 mtdcr(SDRAM_CONF1LL, CONFIG_SYS_SDRAM_CONF1LL);
2866 mtdcr(SDRAM_CONF1HB, CONFIG_SYS_SDRAM_CONF1HB);
2867 mtdcr(SDRAM_CONFPATHB, CONFIG_SYS_SDRAM_CONFPATHB);
2868#endif
2869
Grant Ericksonb6933412008-05-22 14:44:14 -07002870 /* Set Memory Bank Configuration Registers */
2871
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02002872 mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
2873 mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
2874 mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
2875 mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
Grant Ericksonb6933412008-05-22 14:44:14 -07002876
2877 /* Set Memory Clock Timing Register */
2878
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02002879 mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
Grant Ericksonb6933412008-05-22 14:44:14 -07002880
2881 /* Set Refresh Time Register */
2882
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02002883 mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
Grant Ericksonb6933412008-05-22 14:44:14 -07002884
2885 /* Set SDRAM Timing Registers */
2886
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02002887 mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
2888 mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
2889 mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
Grant Ericksonb6933412008-05-22 14:44:14 -07002890
2891 /* Set Mode and Extended Mode Registers */
2892
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02002893 mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
2894 mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
Grant Ericksonb6933412008-05-22 14:44:14 -07002895
2896 /* Set Memory Controller Options 1 Register */
2897
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02002898 mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
Grant Ericksonb6933412008-05-22 14:44:14 -07002899
2900 /* Set Manual Initialization Control Registers */
2901
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02002902 mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
2903 mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
2904 mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
2905 mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
2906 mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
2907 mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
2908 mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
2909 mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
2910 mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
2911 mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
2912 mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
2913 mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
2914 mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
2915 mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
2916 mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
2917 mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
Grant Ericksonb6933412008-05-22 14:44:14 -07002918
2919 /* Set On-Die Termination Registers */
2920
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02002921 mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
2922 mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
2923 mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
Grant Ericksonb6933412008-05-22 14:44:14 -07002924
2925 /* Set Write Timing Register */
2926
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02002927 mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
Grant Ericksonb6933412008-05-22 14:44:14 -07002928
2929 /*
2930 * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
2931 * SDRAM0_MCOPT2[IPTR] = 1
2932 */
2933
2934 mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
2935 SDRAM_MCOPT2_IPTR_EXECUTE));
2936
2937 /*
2938 * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
2939 * completion of initialization.
2940 */
2941
2942 do {
2943 mfsdram(SDRAM_MCSTAT, val);
2944 } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
2945
2946 /* Set Delay Control Registers */
2947
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02002948 mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
Adam Graham97a55812008-09-03 12:26:59 -07002949
2950#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02002951 mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
2952 mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
2953 mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
Adam Graham97a55812008-09-03 12:26:59 -07002954#endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
Grant Ericksonb6933412008-05-22 14:44:14 -07002955
2956 /*
2957 * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
2958 */
2959
2960 mfsdram(SDRAM_MCOPT2, val);
2961 mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
2962
Adam Graham446eb8d2008-10-08 10:13:14 -07002963#if defined(CONFIG_440)
2964 /*
2965 * Program TLB entries with caches enabled, for best performace
2966 * while auto-calibrating and ECC generation
2967 */
2968 program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
2969#endif
2970
Adam Graham97a55812008-09-03 12:26:59 -07002971#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2972#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
2973 /*------------------------------------------------------------------
2974 | DQS calibration.
2975 +-----------------------------------------------------------------*/
2976 DQS_autocalibration();
2977#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
2978#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
2979
Stefan Roesec3bcfce2010-05-25 15:33:14 +02002980 /*
2981 * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2982 * PowerPC440SP/SPe DDR2 application note:
2983 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2984 */
2985 update_rdcc();
2986
Grant Ericksonb6933412008-05-22 14:44:14 -07002987#if defined(CONFIG_DDR_ECC)
Felix Radensky0e925362009-09-27 23:56:12 +02002988 do_program_ecc(0);
Grant Ericksonb6933412008-05-22 14:44:14 -07002989#endif /* defined(CONFIG_DDR_ECC) */
Grant Erickson9416cd92008-07-09 16:46:35 -07002990
Adam Graham446eb8d2008-10-08 10:13:14 -07002991#if defined(CONFIG_440)
2992 /*
2993 * Now after initialization (auto-calibration and ECC generation)
2994 * remove the TLB entries with caches enabled and program again with
2995 * desired cache functionality
2996 */
2997 remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
2998 program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
2999#endif
3000
Grant Erickson9416cd92008-07-09 16:46:35 -07003001 ppc4xx_ibm_ddr2_register_dump();
Adam Graham97a55812008-09-03 12:26:59 -07003002
3003#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3004 /*
3005 * Clear potential errors resulting from auto-calibration.
3006 * If not done, then we could get an interrupt later on when
3007 * exceptions are enabled.
3008 */
3009 set_mcsr(get_mcsr());
3010#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3011
Stefan Roesea226c852008-06-02 17:13:55 +02003012#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
Grant Ericksonb6933412008-05-22 14:44:14 -07003013
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02003014 return (CONFIG_SYS_MBYTES_SDRAM << 20);
Grant Ericksonb6933412008-05-22 14:44:14 -07003015}
Stefan Roese2001a332008-07-10 15:32:32 +02003016#endif /* CONFIG_SPD_EEPROM */
Grant Erickson9416cd92008-07-09 16:46:35 -07003017
Adam Graham97a55812008-09-03 12:26:59 -07003018#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3019#if defined(CONFIG_440)
3020u32 mfdcr_any(u32 dcr)
3021{
3022 u32 val;
3023
3024 switch (dcr) {
3025 case SDRAM_R0BAS + 0:
3026 val = mfdcr(SDRAM_R0BAS + 0);
3027 break;
3028 case SDRAM_R0BAS + 1:
3029 val = mfdcr(SDRAM_R0BAS + 1);
3030 break;
3031 case SDRAM_R0BAS + 2:
3032 val = mfdcr(SDRAM_R0BAS + 2);
3033 break;
3034 case SDRAM_R0BAS + 3:
3035 val = mfdcr(SDRAM_R0BAS + 3);
3036 break;
3037 default:
3038 printf("DCR %d not defined in case statement!!!\n", dcr);
3039 val = 0; /* just to satisfy the compiler */
3040 }
3041
3042 return val;
3043}
3044
3045void mtdcr_any(u32 dcr, u32 val)
3046{
3047 switch (dcr) {
3048 case SDRAM_R0BAS + 0:
3049 mtdcr(SDRAM_R0BAS + 0, val);
3050 break;
3051 case SDRAM_R0BAS + 1:
3052 mtdcr(SDRAM_R0BAS + 1, val);
3053 break;
3054 case SDRAM_R0BAS + 2:
3055 mtdcr(SDRAM_R0BAS + 2, val);
3056 break;
3057 case SDRAM_R0BAS + 3:
3058 mtdcr(SDRAM_R0BAS + 3, val);
3059 break;
3060 default:
3061 printf("DCR %d not defined in case statement!!!\n", dcr);
3062 }
3063}
3064#endif /* defined(CONFIG_440) */
Adam Graham97a55812008-09-03 12:26:59 -07003065#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
3066
3067inline void ppc4xx_ibm_ddr2_register_dump(void)
Grant Erickson9416cd92008-07-09 16:46:35 -07003068{
Stefan Roese2001a332008-07-10 15:32:32 +02003069#if defined(DEBUG)
Grant Erickson9416cd92008-07-09 16:46:35 -07003070 printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3071
3072#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3073 defined(CONFIG_460EX) || defined(CONFIG_460GT))
Felix Radensky8d4d4a62009-07-01 11:37:46 +03003074 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R0BAS);
3075 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R1BAS);
3076 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R2BAS);
3077 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R3BAS);
Grant Erickson9416cd92008-07-09 16:46:35 -07003078#endif /* (defined(CONFIG_440SP) || ... */
3079#if defined(CONFIG_405EX)
3080 PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
3081 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
3082 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
3083 PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
3084 PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
3085 PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
3086#endif /* defined(CONFIG_405EX) */
3087 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
3088 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
3089 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
3090 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
3091 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
3092 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
3093 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
3094 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
3095 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
3096 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
3097 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
3098 PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
3099#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3100 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3101 PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
3102 PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
3103 /*
3104 * OPART is only used as a trigger register.
3105 *
3106 * No data is contained in this register, and reading or writing
3107 * to is can cause bad things to happen (hangs). Just skip it and
3108 * report "N/A".
3109 */
3110 printf("%20s = N/A\n", "SDRAM_OPART");
3111#endif /* defined(CONFIG_440SP) || ... */
3112 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
3113 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
3114 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
3115 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
3116 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
3117 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
3118 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
3119 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
3120 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
3121 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
3122 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
3123 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
3124 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
3125 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
3126 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
3127 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
3128 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
3129 PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
3130 PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
3131 PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
3132 PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
3133 PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
3134 PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
3135 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
3136 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
3137 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
3138 PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
3139 PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
Stefan Roese37748882009-11-03 14:34:45 +01003140 PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCES);
Grant Erickson9416cd92008-07-09 16:46:35 -07003141#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3142 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3143 PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
3144#endif /* defined(CONFIG_440SP) || ... */
3145 PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
3146 PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
3147 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
Stefan Roese2001a332008-07-10 15:32:32 +02003148#endif /* defined(DEBUG) */
3149}