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Eran Liberty9095d4a2005-07-28 10:08:46 -05001#
Marian Balakowiczd62379d2006-09-01 19:49:50 +02002# (C) Copyright 2006
3# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Wolfgang Denk4df0da52006-10-09 00:42:01 +02004#
Eran Liberty9095d4a2005-07-28 10:08:46 -05005# Copyright 2004 Freescale Semiconductor, Inc.
6#
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007# SPDX-License-Identifier: GPL-2.0+
Eran Liberty9095d4a2005-07-28 10:08:46 -05008#
9
Scott Wood2b36fbb2012-12-06 13:33:17 +000010MINIMAL=
11
12ifdef CONFIG_SPL_BUILD
13ifdef CONFIG_SPL_INIT_MINIMAL
14MINIMAL=y
15endif
16endif
17
Masahiro Yamada4fbb29d2013-10-17 17:35:04 +090018extra-y = start.o
Anton Vorontsov6e4404d2008-03-24 17:40:27 +030019
Scott Wood2b36fbb2012-12-06 13:33:17 +000020ifdef MINIMAL
21
Masahiro Yamada4fbb29d2013-10-17 17:35:04 +090022obj-y += spl_minimal.o
Scott Wood2b36fbb2012-12-06 13:33:17 +000023
24else
25
Masahiro Yamada4fbb29d2013-10-17 17:35:04 +090026obj-y += traps.o
27obj-y += cpu.o
28obj-y += cpu_init.o
29obj-y += speed.o
30obj-y += interrupts.o
31obj-y += ecc.o
32obj-$(CONFIG_QE) += qe_io.o
33obj-$(CONFIG_FSL_SERDES) += serdes.o
34obj-$(CONFIG_PCI) += pci.o
35obj-$(CONFIG_PCIE) += pcie.o
36obj-$(CONFIG_OF_LIBFDT) += fdt.o
Eran Liberty9095d4a2005-07-28 10:08:46 -050037
Marek Vasut594f17e2012-05-25 16:14:46 +020038# Stub implementations of cache management functions for USB
Masahiro Yamada4fbb29d2013-10-17 17:35:04 +090039obj-y += cache.o
Marek Vasut594f17e2012-05-25 16:14:46 +020040
York Sune12ce982011-08-26 11:32:44 -070041ifdef CONFIG_FSL_DDR2
Masahiro Yamada4fbb29d2013-10-17 17:35:04 +090042obj-$(CONFIG_MPC8349) += ddr-gen2.o
43SRCS += $(obj)ddr-gen2.c
York Sune12ce982011-08-26 11:32:44 -070044else
Masahiro Yamada4fbb29d2013-10-17 17:35:04 +090045obj-y += spd_sdram.o
York Sune12ce982011-08-26 11:32:44 -070046endif
Masahiro Yamada4fbb29d2013-10-17 17:35:04 +090047obj-$(CONFIG_FSL_DDR2) += law.o
York Sune12ce982011-08-26 11:32:44 -070048
Scott Wood2b36fbb2012-12-06 13:33:17 +000049endif # not minimal
50
York Sune12ce982011-08-26 11:32:44 -070051$(obj)ddr-gen1.c:
York Sune12ce982011-08-26 11:32:44 -070052 ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen1.c $(obj)ddr-gen1.c
53
54$(obj)ddr-gen2.c:
York Sune12ce982011-08-26 11:32:44 -070055 ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen2.c $(obj)ddr-gen2.c
56
57$(obj)ddr-gen3.c:
York Sune12ce982011-08-26 11:32:44 -070058 ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen3.c $(obj)ddr-gen3.c