blob: 228adda0aa8bf521d5e4a29a74473e7d9f29cb17 [file] [log] [blame]
Stephen Warrenfccc9c52016-08-08 11:28:25 -06001/*
2 * Copyright (c) 2016, NVIDIA CORPORATION.
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#include <common.h>
8#include <dm.h>
9#include <misc.h>
10#include <reset-uclass.h>
11#include <asm/arch-tegra/bpmp_abi.h>
12
13static int tegra186_reset_request(struct reset_ctl *reset_ctl)
14{
15 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
16 reset_ctl->dev, reset_ctl->id);
17
18 return 0;
19}
20
21static int tegra186_reset_free(struct reset_ctl *reset_ctl)
22{
23 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
24 reset_ctl->dev, reset_ctl->id);
25
26 return 0;
27}
28
29static int tegra186_reset_common(struct reset_ctl *reset_ctl,
30 enum mrq_reset_commands cmd)
31{
32 struct mrq_reset_request req;
33 int ret;
34
35 req.cmd = cmd;
36 req.reset_id = reset_ctl->id;
37
38 ret = misc_call(reset_ctl->dev->parent, MRQ_RESET, &req, sizeof(req),
39 NULL, 0);
40 if (ret < 0)
41 return ret;
42
43 return 0;
44}
45
46static int tegra186_reset_assert(struct reset_ctl *reset_ctl)
47{
48 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
49 reset_ctl->dev, reset_ctl->id);
50
51 return tegra186_reset_common(reset_ctl, CMD_RESET_ASSERT);
52}
53
54static int tegra186_reset_deassert(struct reset_ctl *reset_ctl)
55{
56 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
57 reset_ctl->dev, reset_ctl->id);
58
59 return tegra186_reset_common(reset_ctl, CMD_RESET_DEASSERT);
60}
61
62struct reset_ops tegra186_reset_ops = {
63 .request = tegra186_reset_request,
64 .free = tegra186_reset_free,
65 .rst_assert = tegra186_reset_assert,
66 .rst_deassert = tegra186_reset_deassert,
67};
68
69static int tegra186_reset_probe(struct udevice *dev)
70{
71 debug("%s(dev=%p)\n", __func__, dev);
72
73 return 0;
74}
75
76U_BOOT_DRIVER(tegra186_reset) = {
77 .name = "tegra186_reset",
78 .id = UCLASS_RESET,
79 .probe = tegra186_reset_probe,
80 .ops = &tegra186_reset_ops,
81};