| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| Stefan Roese | e373c5f | 2009-01-21 17:24:49 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering |
| 4 | * |
| 5 | * Original Author Guenter Gebhardt |
| 6 | * Copyright (C) 2006 Micronas GmbH |
| Stefan Roese | e373c5f | 2009-01-21 17:24:49 +0100 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | |
| 11 | #include "vct.h" |
| 12 | |
| 13 | int vct_ehci_hcd_init(u32 *hccr, u32 *hcor) |
| 14 | { |
| 15 | int retval; |
| 16 | u32 val; |
| 17 | u32 addr; |
| 18 | |
| 19 | dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON); |
| 20 | dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON); |
| 21 | dcgu_set_clk_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON); |
| 22 | dcgu_set_clk_switch(DCGU_HW_MODULE_USB_PLL, DCGU_SWITCH_ON); |
| 23 | dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_OFF); |
| 24 | |
| 25 | /* Wait until (DCGU_USBPHY_STAT == 7) */ |
| 26 | addr = DCGU_USBPHY_STAT(DCGU_BASE); |
| 27 | val = reg_read(addr); |
| 28 | while (val != 7) |
| 29 | val = reg_read(addr); |
| 30 | |
| 31 | dcgu_set_clk_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON); |
| 32 | dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_OFF); |
| 33 | |
| 34 | retval = scc_reset(SCC_USB_RW, 0); |
| 35 | if (retval) { |
| 36 | printf("scc_reset(SCC_USB_RW, 0) returned: 0x%x\n", retval); |
| 37 | return retval; |
| 38 | } else { |
| 39 | retval = scc_reset(SCC_CPU1_SPDMA_RW, 0); |
| 40 | if (retval) { |
| 41 | printf("scc_reset(SCC_CPU1_SPDMA_RW, 0) returned: 0x%x\n", |
| 42 | retval); |
| 43 | return retval; |
| 44 | } |
| 45 | } |
| 46 | |
| 47 | if (!retval) { |
| 48 | /* |
| 49 | * For the AGU bypass, where the SCC client provides full |
| 50 | * physical address |
| 51 | */ |
| 52 | scc_set_usb_address_generation_mode(1); |
| 53 | scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_1, DMA_LINEAR, |
| 54 | USE_NO_FH, DMA_READ, 0); |
| 55 | scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_1, DMA_LINEAR, |
| 56 | USE_NO_FH, DMA_WRITE, 0); |
| 57 | scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_0, DMA_LINEAR, |
| 58 | USE_NO_FH, DMA_WRITE, 0); |
| 59 | scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_0, DMA_LINEAR, |
| 60 | USE_NO_FH, DMA_READ, 0); |
| 61 | |
| 62 | /* Enable memory interface */ |
| 63 | scc_enable(SCC_USB_RW, 1); |
| 64 | |
| 65 | /* Start (start_cmd=0) DMAs */ |
| 66 | scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_READ); |
| 67 | scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_WRITE); |
| 68 | } else { |
| 69 | printf("Cannot configure USB memory channel.\n"); |
| 70 | printf("USB can not access RAM. SCC configuration failed.\n"); |
| 71 | return retval; |
| 72 | } |
| 73 | |
| 74 | /* Wait a short while */ |
| 75 | udelay(300000); |
| 76 | |
| 77 | reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c); |
| 78 | |
| 79 | /* Set EHCI structures and DATA in RAM */ |
| 80 | reg_write(USBH_USBHMISC(USBH_BASE), 0x00840003); |
| 81 | /* Set USBMODE to bigendian and set host mode */ |
| 82 | reg_write(USBH_USBMODE(USBH_BASE), 0x00000007); |
| 83 | |
| 84 | /* |
| 85 | * USBH_BURSTSIZE MUST EQUAL 0x00001c1c in order for |
| 86 | * 512 byte USB transfers on the bulk pipe to work properly. |
| 87 | * Set USBH_BURSTSIZE to 0x00001c1c |
| 88 | */ |
| 89 | reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c); |
| 90 | |
| 91 | /* Insert access register addresses */ |
| 92 | *hccr = REG_GLOBAL_START_ADDR + USBH_CAPLENGTH(USBH_BASE); |
| 93 | *hcor = REG_GLOBAL_START_ADDR + USBH_USBCMD(USBH_BASE); |
| 94 | |
| 95 | return 0; |
| 96 | } |