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Tom Rix3db7af72009-09-27 07:47:24 -05001/*
Eric Bénard62d2b622010-08-09 11:50:45 +02002 * CPUAT91 by (C) Copyright 2006-2010 Eric Benard
Tom Rix3db7af72009-09-27 07:47:24 -05003 * eric@eukrea.com
4 *
5 * Configuration settings for the CPUAT91 board.
6 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Tom Rix3db7af72009-09-27 07:47:24 -05008 */
9
Eric Bénard62d2b622010-08-09 11:50:45 +020010#ifndef _CONFIG_CPUAT91_H
11#define _CONFIG_CPUAT91_H
Jens Scharsig128ecd02010-02-03 22:45:42 +010012
Eric Benardc2e1f232011-04-03 06:35:55 +000013#include <asm/sizes.h>
14
15#ifdef CONFIG_RAMBOOT
16#define CONFIG_SKIP_LOWLEVEL_INIT
17#define CONFIG_SYS_TEXT_BASE 0x21F00000
Tom Rix3db7af72009-09-27 07:47:24 -050018#else
19#define CONFIG_BOOTDELAY 1
Eric Benardc2e1f232011-04-03 06:35:55 +000020#define CONFIG_SYS_TEXT_BASE 0
Tom Rix3db7af72009-09-27 07:47:24 -050021#endif
22
Eric Benardc2e1f232011-04-03 06:35:55 +000023#define AT91C_XTAL_CLOCK 18432000
Andreas Bießmannc2a1f0f2011-06-12 01:49:12 +000024#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
Eric Benardc2e1f232011-04-03 06:35:55 +000025#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39)
26#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3)
27#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
28#define CONFIG_SYS_HZ 1000
Tom Rix3db7af72009-09-27 07:47:24 -050029
Eric Benardc2e1f232011-04-03 06:35:55 +000030#define CONFIG_ARM920T
31#define CONFIG_AT91RM9200
32#define CONFIG_CPUAT91
Eric Benardc2e1f232011-04-03 06:35:55 +000033#define USE_920T_MMU
Tom Rix3db7af72009-09-27 07:47:24 -050034
Andreas Bießmannc2a1f0f2011-06-12 01:49:12 +000035#include <asm/hardware.h> /* needed for port definitions */
36
Eric Benardc2e1f232011-04-03 06:35:55 +000037#define CONFIG_CMDLINE_TAG
38#define CONFIG_SETUP_MEMORY_TAGS
39#define CONFIG_INITRD_TAG
Andreas Bießmanna631d2b2011-06-12 01:49:16 +000040#define CONFIG_BOARD_EARLY_INIT_F
Tom Rix3db7af72009-09-27 07:47:24 -050041
42#ifndef CONFIG_SKIP_LOWLEVEL_INIT
Eric Benardc2e1f232011-04-03 06:35:55 +000043#define CONFIG_SYS_USE_MAIN_OSCILLATOR
Tom Rix3db7af72009-09-27 07:47:24 -050044/* flash */
45#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
46#define CONFIG_SYS_MC_PUP_VAL 0x00000000
47#define CONFIG_SYS_MC_PUER_VAL 0x00000000
48#define CONFIG_SYS_MC_ASR_VAL 0x00000000
49#define CONFIG_SYS_MC_AASR_VAL 0x00000000
50#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
51#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
52
53/* clocks */
54#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
55#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz for USB */
56#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock */
57
58/* sdram */
59#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as D16/D31 */
60#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
61#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
62#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
63#define CONFIG_SYS_SDRC_CR_VAL 0x2188C155 /* set up the SDRAM */
64#define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */
65#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */
66#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */
67#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
68#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
69#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
70#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
71#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
72#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
73
Andreas Bießmanna631d2b2011-06-12 01:49:16 +000074#define CONFIG_ATMEL_USART
75#define CONFIG_USART_BASE ATMEL_BASE_DBGU
76#define CONFIG_USART_ID 0/* ignored in arm */
Tom Rix3db7af72009-09-27 07:47:24 -050077
Eric Bénard62d2b622010-08-09 11:50:45 +020078#undef CONFIG_HARD_I2C
Eric Bénard62d2b622010-08-09 11:50:45 +020079#define AT91_PIN_SDA (1<<25)
80#define AT91_PIN_SCL (1<<26)
81
Eric Benardc2e1f232011-04-03 06:35:55 +000082#define CONFIG_SYS_I2C_INIT_BOARD
Eric Bénard62d2b622010-08-09 11:50:45 +020083#define CONFIG_SYS_I2C_SPEED 50000
84#define CONFIG_SYS_I2C_SLAVE 0
Tom Rix3db7af72009-09-27 07:47:24 -050085
Eric Bénard62d2b622010-08-09 11:50:45 +020086#define I2C_INIT i2c_init_board();
87#define I2C_ACTIVE writel(AT91_PMX_AA_TWD, &pio->pioa.mddr);
88#define I2C_TRISTATE writel(AT91_PMX_AA_TWD, &pio->pioa.mder);
89#define I2C_READ ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0)
90#define I2C_SDA(bit) \
91 if (bit) \
92 writel(AT91_PMX_AA_TWD, &pio->pioa.sodr); \
93 else \
94 writel(AT91_PMX_AA_TWD, &pio->pioa.codr);
95#define I2C_SCL(bit) \
96 if (bit) \
97 writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr); \
98 else \
99 writel(AT91_PMX_AA_TWCK, &pio->pioa.codr);
100
101#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
102
Tom Rix3db7af72009-09-27 07:47:24 -0500103#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
104#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
105#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1
106#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Tom Rix3db7af72009-09-27 07:47:24 -0500107
Eric Benardc2e1f232011-04-03 06:35:55 +0000108#define CONFIG_BOOTP_BOOTFILESIZE
109#define CONFIG_BOOTP_BOOTPATH
110#define CONFIG_BOOTP_GATEWAY
111#define CONFIG_BOOTP_HOSTNAME
Tom Rix3db7af72009-09-27 07:47:24 -0500112
113#include <config_cmd_default.h>
114
Eric Benardc2e1f232011-04-03 06:35:55 +0000115#define CONFIG_CMD_PING
116#define CONFIG_CMD_MII
117#define CONFIG_CMD_CACHE
Tom Rix3db7af72009-09-27 07:47:24 -0500118#undef CONFIG_CMD_USB
119#undef CONFIG_CMD_FPGA
120#undef CONFIG_CMD_IMI
121#undef CONFIG_CMD_LOADS
122#undef CONFIG_CMD_NFS
Eric Benardc2e1f232011-04-03 06:35:55 +0000123#undef CONFIG_CMD_DHCP
Tom Rix3db7af72009-09-27 07:47:24 -0500124
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100125#ifdef CONFIG_SYS_I2C_SOFT
Eric Benardc2e1f232011-04-03 06:35:55 +0000126#define CONFIG_CMD_EEPROM
127#define CONFIG_CMD_I2C
128#endif
Tom Rix3db7af72009-09-27 07:47:24 -0500129
130#define CONFIG_NR_DRAM_BANKS 1
Eric Benardc2e1f232011-04-03 06:35:55 +0000131#define CONFIG_SYS_SDRAM_BASE 0x20000000
132#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
Tom Rix3db7af72009-09-27 07:47:24 -0500133
Eric Benardc2e1f232011-04-03 06:35:55 +0000134#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
Tom Rix3db7af72009-09-27 07:47:24 -0500135#define CONFIG_SYS_MEMTEST_END \
Eric Benardc2e1f232011-04-03 06:35:55 +0000136 (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
Tom Rix3db7af72009-09-27 07:47:24 -0500137
Eric Benardc2e1f232011-04-03 06:35:55 +0000138#define CONFIG_DRIVER_AT91EMAC
139#define CONFIG_SYS_RX_ETH_BUFFER 16
140#define CONFIG_RMII
141#define CONFIG_MII
Eric Bénard58633c12010-06-21 09:40:43 +0200142#define CONFIG_DRIVER_AT91EMAC_PHYADDR 1
Tom Rix3db7af72009-09-27 07:47:24 -0500143#define CONFIG_NET_RETRY_COUNT 20
Eric Benardc2e1f232011-04-03 06:35:55 +0000144#define CONFIG_KS8721_PHY
Tom Rix3db7af72009-09-27 07:47:24 -0500145
Eric Benardc2e1f232011-04-03 06:35:55 +0000146#define CONFIG_SYS_FLASH_CFI
147#define CONFIG_FLASH_CFI_DRIVER
148#define CONFIG_SYS_FLASH_EMPTY_INFO
149#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Tom Rix3db7af72009-09-27 07:47:24 -0500150#define CONFIG_SYS_MAX_FLASH_BANKS 1
Eric Benardc2e1f232011-04-03 06:35:55 +0000151#define CONFIG_SYS_FLASH_PROTECTION
Tom Rix3db7af72009-09-27 07:47:24 -0500152#define PHYS_FLASH_1 0x10000000
153#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
154#define CONFIG_SYS_MAX_FLASH_SECT 128
Eric Bénard62d2b622010-08-09 11:50:45 +0200155#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Eric Benardc2e1f232011-04-03 06:35:55 +0000156#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
157#define PHYS_FLASH_SIZE (16 * 1024 * 1024)
158#define CONFIG_SYS_FLASH_BANKS_LIST \
159 { PHYS_FLASH_1 }
Tom Rix3db7af72009-09-27 07:47:24 -0500160
161#if defined(CONFIG_CMD_USB)
Eric Benardc2e1f232011-04-03 06:35:55 +0000162#define CONFIG_USB_ATMEL
Bo Shen4a985df2013-10-21 16:14:00 +0800163#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Eric Benardc2e1f232011-04-03 06:35:55 +0000164#define CONFIG_USB_OHCI_NEW
165#define CONFIG_USB_STORAGE
166#define CONFIG_DOS_PARTITION
167#define CONFIG_AT91C_PQFP_UHPBU
Tom Rix3db7af72009-09-27 07:47:24 -0500168#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
Eric Benardc2e1f232011-04-03 06:35:55 +0000169#define CONFIG_SYS_USB_OHCI_CPU_INIT
Tom Rix3db7af72009-09-27 07:47:24 -0500170#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
171#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
172#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
173#endif
174
Eric Benardc2e1f232011-04-03 06:35:55 +0000175#define CONFIG_ENV_IS_IN_FLASH
176#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 128 * 1024)
177#define CONFIG_ENV_SIZE (128 * 1024)
178#define CONFIG_ENV_SECT_SIZE (128 * 1024)
Tom Rix3db7af72009-09-27 07:47:24 -0500179
180#define CONFIG_SYS_LOAD_ADDR 0x21000000
181
182#define CONFIG_BAUDRATE 115200
Tom Rix3db7af72009-09-27 07:47:24 -0500183
184#define CONFIG_SYS_PROMPT "CPUAT91=> "
185#define CONFIG_SYS_CBSIZE 256
186#define CONFIG_SYS_MAXARGS 32
187#define CONFIG_SYS_PBSIZE \
188 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Eric Benardc2e1f232011-04-03 06:35:55 +0000189#define CONFIG_CMDLINE_EDITING
Tom Rix3db7af72009-09-27 07:47:24 -0500190
Eric Benardc2e1f232011-04-03 06:35:55 +0000191#define CONFIG_SYS_MALLOC_LEN \
192 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 4 * 1024)
Tom Rix3db7af72009-09-27 07:47:24 -0500193
Eric Benardc2e1f232011-04-03 06:35:55 +0000194#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
195 GENERATED_GBL_DATA_SIZE)
196
Eric Benardc2e1f232011-04-03 06:35:55 +0000197#define CONFIG_DEVICE_NULLDEV
198#define CONFIG_SILENT_CONSOLE
Tom Rix3db7af72009-09-27 07:47:24 -0500199
Eric Benardc2e1f232011-04-03 06:35:55 +0000200#define CONFIG_AUTOBOOT_KEYED
Eric Benard14790262009-10-12 10:15:39 +0200201#define CONFIG_AUTOBOOT_PROMPT \
202 "Press SPACE to abort autoboot\n"
Tom Rix3db7af72009-09-27 07:47:24 -0500203#define CONFIG_AUTOBOOT_STOP_STR " "
204#define CONFIG_AUTOBOOT_DELAY_STR "d"
205
Eric Benardc2e1f232011-04-03 06:35:55 +0000206#define CONFIG_VERSION_VARIABLE
Tom Rix3db7af72009-09-27 07:47:24 -0500207
208#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
209#define MTDPARTS_DEFAULT \
210 "mtdparts=physmap-flash.0:" \
211 "128k(u-boot)ro," \
212 "128k(u-boot-env)," \
Eric Bénard56a5fb02010-08-09 11:50:46 +0200213 "1792k(kernel)," \
Tom Rix3db7af72009-09-27 07:47:24 -0500214 "-(rootfs)"
215
216#define CONFIG_BOOTARGS \
217 "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,115200"
218
219#define CONFIG_BOOTCOMMAND "run flashboot"
220
221#define CONFIG_EXTRA_ENV_SETTINGS \
222 "mtdid=" MTDIDS_DEFAULT "\0" \
223 "mtdparts=" MTDPARTS_DEFAULT "\0" \
224 "flub=tftp 21000000 cpuat91/u-boot.bin; protect off 10000000 " \
225 "1001FFFF; erase 10000000 1001FFFF; cp.b 21000000 " \
226 "10000000 ${filesize}\0" \
227 "flui=tftp 21000000 cpuat91/uImage; protect off 10040000 " \
Eric Bénard56a5fb02010-08-09 11:50:46 +0200228 "1019ffff; erase 10040000 101fffff; cp.b 21000000 " \
Tom Rix3db7af72009-09-27 07:47:24 -0500229 "10040000 ${filesize}\0" \
230 "flrfs=tftp 21000000 cpuat91/rootfs.jffs2; protect off " \
Eric Bénard56a5fb02010-08-09 11:50:46 +0200231 "10200000 10ffffff; erase 10200000 10ffffff; cp.b " \
232 "21000000 10200000 ${filesize}\0" \
Tom Rix3db7af72009-09-27 07:47:24 -0500233 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
234 "flashboot=run ramargs;bootm 10040000\0" \
235 "netboot=run ramargs;tftpboot 21000000 cpuat91/uImage;" \
236 "bootm 21000000\0"
Eric Bénard62d2b622010-08-09 11:50:45 +0200237#endif /* _CONFIG_CPUAT91_H */