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Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +01001/*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * Configuration settings for the ATSTK1003 CPU daughterboard
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +01007 */
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Andreas Bießmann94156fa2010-11-04 23:15:30 +000011#include <asm/arch/hardware.h>
Haavard Skinnemoen23f62f12008-05-19 11:36:28 +020012
Andreas Bießmann36131452011-04-18 04:12:38 +000013#define CONFIG_AVR32
14#define CONFIG_AT32AP
15#define CONFIG_AT32AP7002
16#define CONFIG_ATSTK1004
17#define CONFIG_ATSTK1000
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +010018
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +010019/*
20 * Timer clock frequency. We're using the CPU-internal COUNT register
21 * for this, so this is equivalent to the CPU core clock frequency
22 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020023#define CONFIG_SYS_HZ 1000
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +010024
25/*
26 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
27 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
28 * PLL frequency.
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020029 * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +010030 */
Andreas Bießmann36131452011-04-18 04:12:38 +000031#define CONFIG_PLL
32#define CONFIG_SYS_POWER_MANAGER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020033#define CONFIG_SYS_OSC0_HZ 20000000
34#define CONFIG_SYS_PLL0_DIV 1
35#define CONFIG_SYS_PLL0_MUL 7
36#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +010037/*
38 * Set the CPU running at:
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020039 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +010040 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020041#define CONFIG_SYS_CLKDIV_CPU 0
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +010042/*
43 * Set the HSB running at:
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020044 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +010045 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020046#define CONFIG_SYS_CLKDIV_HSB 1
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +010047/*
48 * Set the PBA running at:
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020049 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +010050 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020051#define CONFIG_SYS_CLKDIV_PBA 2
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +010052/*
53 * Set the PBB running at:
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020054 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +010055 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020056#define CONFIG_SYS_CLKDIV_PBB 1
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +010057
Haavard Skinnemoenc6f292f2010-08-12 13:52:54 +070058/* Reserve VM regions for SDRAM and NOR flash */
59#define CONFIG_SYS_NR_VM_REGIONS 2
60
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +010061/*
62 * The PLLOPT register controls the PLL like this:
63 * icp = PLLOPT<2>
64 * ivco = PLLOPT<1:0>
65 *
66 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
67 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020068#define CONFIG_SYS_PLL0_OPT 0x04
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +010069
Andreas Bießmann5807e792010-11-04 23:15:31 +000070#define CONFIG_USART_BASE ATMEL_BASE_USART1
71#define CONFIG_USART_ID 1
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +010072
73/* User serviceable stuff */
Andreas Bießmann36131452011-04-18 04:12:38 +000074#define CONFIG_DOS_PARTITION
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +010075
Andreas Bießmann36131452011-04-18 04:12:38 +000076#define CONFIG_CMDLINE_TAG
77#define CONFIG_SETUP_MEMORY_TAGS
78#define CONFIG_INITRD_TAG
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +010079
80#define CONFIG_STACKSIZE (2048)
81
82#define CONFIG_BAUDRATE 115200
83#define CONFIG_BOOTARGS \
84 "console=ttyS0 root=/dev/mmcblk0p1 rootwait"
85
86#define CONFIG_BOOTCOMMAND \
Sven Schnelle8aa96822011-10-21 14:49:25 +020087 "mmc rescan; ext2load mmc 0:1 0x10200000 /boot/uImage; bootm"
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +010088
89/*
90 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
91 * data on the serial line may interrupt the boot sequence.
92 */
93#define CONFIG_BOOTDELAY 1
Andreas Bießmann36131452011-04-18 04:12:38 +000094#define CONFIG_AUTOBOOT
95#define CONFIG_AUTOBOOT_KEYED
Wolfgang Denkdd5463b2008-07-16 16:38:59 +020096#define CONFIG_AUTOBOOT_PROMPT \
97 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +010098#define CONFIG_AUTOBOOT_DELAY_STR "d"
99#define CONFIG_AUTOBOOT_STOP_STR " "
100
101/*
102 * Command line configuration.
103 */
104#include <config_cmd_default.h>
105
106#define CONFIG_CMD_ASKENV
107#define CONFIG_CMD_EXT2
108#define CONFIG_CMD_FAT
109#define CONFIG_CMD_JFFS2
110#define CONFIG_CMD_MMC
111
112#undef CONFIG_CMD_FPGA
113#undef CONFIG_CMD_NET
114#undef CONFIG_CMD_NFS
115#undef CONFIG_CMD_SETGETDCR
116#undef CONFIG_CMD_XIMG
117
Andreas Bießmann36131452011-04-18 04:12:38 +0000118#define CONFIG_ATMEL_USART
119#define CONFIG_PORTMUX_PIO
120#define CONFIG_SYS_HSDRAMC
121#define CONFIG_MMC
Sven Schnelle8aa96822011-10-21 14:49:25 +0200122#define CONFIG_GENERIC_ATMEL_MCI
123#define CONFIG_GENERIC_MMC
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +0100124
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200125#define CONFIG_SYS_DCACHE_LINESZ 32
126#define CONFIG_SYS_ICACHE_LINESZ 32
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +0100127
128#define CONFIG_NR_DRAM_BANKS 1
129
Andreas Bießmannab7344a2011-06-28 04:15:58 +0000130#define CONFIG_SYS_FLASH_CFI
131#define CONFIG_FLASH_CFI_DRIVER
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +0100132
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200133#define CONFIG_SYS_FLASH_BASE 0x00000000
134#define CONFIG_SYS_FLASH_SIZE 0x800000
135#define CONFIG_SYS_MAX_FLASH_BANKS 1
136#define CONFIG_SYS_MAX_FLASH_SECT 135
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +0100137
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200138#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Andreas Bießmann71c2bf52011-04-18 04:12:44 +0000139#define CONFIG_SYS_TEXT_BASE 0x00000000
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +0100140
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200141#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
142#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
143#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +0100144
Andreas Bießmann36131452011-04-18 04:12:38 +0000145#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200146#define CONFIG_ENV_SIZE 65536
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200147#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +0100148
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200149#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +0100150
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200151#define CONFIG_SYS_MALLOC_LEN (256*1024)
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +0100152
Haavard Skinnemoen81634682007-11-22 17:04:13 +0100153/* Allow 2MB for the kernel run-time image */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200154#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00200000)
155#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +0100156
157/* Other configuration settings that shouldn't have to change all that often */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200158#define CONFIG_SYS_PROMPT "U-Boot> "
159#define CONFIG_SYS_CBSIZE 256
160#define CONFIG_SYS_MAXARGS 16
161#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Andreas Bießmann36131452011-04-18 04:12:38 +0000162#define CONFIG_SYS_LONGHELP
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +0100163
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200164#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
165#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
166#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
Haavard Skinnemoen787ef7b2007-10-29 13:02:54 +0100167
168#endif /* __CONFIG_H */