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git01.mediatek.com / filogic / uboot / 4f95d6ec6c9b0a0c596e6e855ecd2a41f3efe796 / . / drivers / net / fm / t4240.c
blob: 6253f22f75de8b938c7aeb25db8e0ae958aae49a [file] [log] [blame]
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Roy Zang <tie-fei.zang@freescale.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]6 */
7#include <common.h>
8#include <phy.h>
9#include <fm_eth.h>
10#include <asm/io.h>
11#include <asm/immap_85xx.h>
12#include <asm/fsl_serdes.h>
13
14u32 port_to_devdisr[] = {
15 [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
16 [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
17 [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
18 [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
19 [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
20 [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
21 [FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
22 [FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
23 [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
24 [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
25 [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
26 [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
27 [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
28 [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
29 [FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5,
30 [FM2_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC2_6,
31 [FM2_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC2_9,
32 [FM2_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC2_10,
33 [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2_1,
34 [FM2_10GEC2] = FSL_CORENET_DEVDISR2_10GEC2_2,
35};
36
37static int is_device_disabled(enum fm_port port)
38{
39 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
40 u32 devdisr2 = in_be32(&gur->devdisr2);
41
42 return port_to_devdisr[port] & devdisr2;
43}
44
45void fman_disable_port(enum fm_port port)
46{
47 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
48
49 setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
50}
51
52phy_interface_t fman_port_enet_if(enum fm_port port)
53{
54 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
55 u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
56
57 if (is_device_disabled(port))
58 return PHY_INTERFACE_MODE_NONE;
59
Shaohui Xief25c70c2013-03-25 07:33:17 +0000[diff] [blame]60 if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
61 ((is_serdes_configured(XAUI_FM1_MAC9)) ||
62 (is_serdes_configured(XAUI_FM1_MAC10)) ||
63 (is_serdes_configured(XFI_FM1_MAC9)) ||
64 (is_serdes_configured(XFI_FM1_MAC10))))
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]65 return PHY_INTERFACE_MODE_XGMII;
66
Shaohui Xief25c70c2013-03-25 07:33:17 +0000[diff] [blame]67 if ((port == FM2_10GEC1 || port == FM2_10GEC2) &&
68 ((is_serdes_configured(XAUI_FM2_MAC9)) ||
69 (is_serdes_configured(XAUI_FM2_MAC10)) ||
70 (is_serdes_configured(XFI_FM2_MAC9)) ||
71 (is_serdes_configured(XFI_FM2_MAC10))))
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]72 return PHY_INTERFACE_MODE_XGMII;
73
74#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
75#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
76#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
77#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
78#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
79#define FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII 0x08000000
80#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
81 /* handle RGMII first */
82 if ((port == FM2_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
83 FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII))
84 return PHY_INTERFACE_MODE_RGMII;
85
86 if ((port == FM1_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
87 FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII))
88 return PHY_INTERFACE_MODE_RGMII;
89
90 if ((port == FM2_DTSEC6) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
91 FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII))
92 return PHY_INTERFACE_MODE_RGMII;
93 switch (port) {
94 case FM1_DTSEC1:
95 case FM1_DTSEC2:
96 case FM1_DTSEC3:
97 case FM1_DTSEC4:
98 case FM1_DTSEC5:
99 case FM1_DTSEC6:
100 case FM1_DTSEC9:
101 case FM1_DTSEC10:
102 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
103 return PHY_INTERFACE_MODE_SGMII;
104 break;
105 case FM2_DTSEC1:
106 case FM2_DTSEC2:
107 case FM2_DTSEC3:
108 case FM2_DTSEC4:
109 case FM2_DTSEC5:
110 case FM2_DTSEC6:
111 case FM2_DTSEC9:
112 case FM2_DTSEC10:
113 if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
114 return PHY_INTERFACE_MODE_SGMII;
115 break;
116 default:
Shaohui Xiec218d292013-08-19 18:58:52 +0800[diff] [blame]117 break;
118 }
119
120 /* handle QSGMII */
121 switch (port) {
122 case FM1_DTSEC1:
123 case FM1_DTSEC2:
124 case FM1_DTSEC3:
125 case FM1_DTSEC4:
126 /* check lane G on SerDes1 */
127 if (is_serdes_configured(QSGMII_FM1_A))
128 return PHY_INTERFACE_MODE_QSGMII;
129 break;
130 case FM1_DTSEC5:
131 case FM1_DTSEC6:
132 case FM1_DTSEC9:
133 case FM1_DTSEC10:
134 /* check lane C on SerDes1 */
135 if (is_serdes_configured(QSGMII_FM1_B))
136 return PHY_INTERFACE_MODE_QSGMII;
137 break;
138 case FM2_DTSEC1:
139 case FM2_DTSEC2:
140 case FM2_DTSEC3:
141 case FM2_DTSEC4:
142 /* check lane G on SerDes2 */
143 if (is_serdes_configured(QSGMII_FM2_A))
144 return PHY_INTERFACE_MODE_QSGMII;
145 break;
146 case FM2_DTSEC5:
147 case FM2_DTSEC6:
148 case FM2_DTSEC9:
149 case FM2_DTSEC10:
150 /* check lane C on SerDes2 */
151 if (is_serdes_configured(QSGMII_FM2_B))
152 return PHY_INTERFACE_MODE_QSGMII;
153 break;
154 default:
155 break;
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]156 }
157
158 return PHY_INTERFACE_MODE_NONE;
159}