blob: 63a403231d6f65210d9fe8980e84cccf44b4e0d5 [file] [log] [blame]
Stefan Roese99200d22005-08-22 17:51:53 +02001/*
2 * (C) Copyright 2004
3 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese99200d22005-08-22 17:51:53 +02006 */
7
8#define SDRAM_DDR 1 /* is DDR */
9
Stefan Roese99200d22005-08-22 17:51:53 +020010/* Settings for XLB = 132 MHz */
11#define SDRAM_MODE 0x018D0000
12#define SDRAM_EMODE 0x40090000
13#define SDRAM_CONTROL 0x705f0f00
14#define SDRAM_CONFIG1 0x73722930
15#define SDRAM_CONFIG2 0x47770000
16#define SDRAM_TAPDELAY 0x10000000