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git01.mediatek.com / filogic / uboot / 4f80e28f160d347957b2f2dfda3a59e7c41dfc6f / . / configs / roc-cc-rk3328_defconfig
blob: 6526d2606e72f151db662026180d4bc3888292b0 [file] [log] [blame]
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]1CONFIG_ARM=y
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]2CONFIG_SKIP_LOWLEVEL_INIT=y
Peng Fanc8a61c02022-04-13 17:47:20 +0800[diff] [blame]3CONFIG_COUNTER_FREQUENCY=24000000
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]4CONFIG_ARCH_ROCKCHIP=y
Simon Glass035939e2021-07-10 21:14:30 -0600[diff] [blame]5CONFIG_SPL_GPIO=y
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]6CONFIG_NR_DRAM_BANKS=1
Tom Rinia77d6f82023-05-01 11:50:26 -0400[diff] [blame]7CONFIG_SF_DEFAULT_SPEED=20000000
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]8CONFIG_ENV_OFFSET=0x3F8000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]9CONFIG_DEFAULT_DEVICE_TREE="rk3328-roc-cc"
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]10CONFIG_DM_RESET=y
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]11CONFIG_ROCKCHIP_RK3328=y
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]12CONFIG_DEBUG_UART_BASE=0xFF130000
13CONFIG_DEBUG_UART_CLOCK=24000000
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]14CONFIG_SYS_LOAD_ADDR=0x800800
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]15CONFIG_DEBUG_UART=y
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]16CONFIG_FIT=y
17CONFIG_FIT_VERBOSE=y
Jonas Karlman4ac67eb2024-02-17 00:22:30 +0000[diff] [blame]18CONFIG_SPL_FIT_SIGNATURE=y
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]19CONFIG_SPL_LOAD_FIT=y
Jonas Karlman4ac67eb2024-02-17 00:22:30 +0000[diff] [blame]20CONFIG_LEGACY_IMAGE_FORMAT=y
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]21CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-roc-cc.dtb"
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]22# CONFIG_DISPLAY_CPUINFO is not set
23CONFIG_DISPLAY_BOARDINFO_LATE=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]24CONFIG_SPL_MAX_SIZE=0x40000
25CONFIG_SPL_PAD_TO=0x7f8000
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]26# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Simon Glasse91ac4c2021-07-10 21:14:24 -0600[diff] [blame]27CONFIG_SPL_POWER=y
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]28CONFIG_SPL_ATF=y
29CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
30CONFIG_CMD_BOOTZ=y
Jonas Karlman4ac67eb2024-02-17 00:22:30 +0000[diff] [blame]31CONFIG_CMD_GPIO=y
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]32CONFIG_CMD_GPT=y
33CONFIG_CMD_MMC=y
Jonas Karlman4ac67eb2024-02-17 00:22:30 +0000[diff] [blame]34CONFIG_CMD_POWEROFF=y
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]35CONFIG_CMD_USB=y
36# CONFIG_CMD_SETEXPR is not set
37CONFIG_CMD_TIME=y
Jonas Karlman4ac67eb2024-02-17 00:22:30 +0000[diff] [blame]38CONFIG_CMD_REGULATOR=y
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]39CONFIG_SPL_OF_CONTROL=y
40CONFIG_TPL_OF_CONTROL=y
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]41CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
42CONFIG_TPL_OF_PLATDATA=y
43CONFIG_ENV_IS_IN_MMC=y
44CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Tom Rinieb1f9092020-07-24 17:14:47 -0400[diff] [blame]45CONFIG_SYS_MMC_ENV_DEV=1
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]46CONFIG_TPL_DM=y
Jonas Karlman4ac67eb2024-02-17 00:22:30 +0000[diff] [blame]47CONFIG_SPL_DM_SEQ_ALIAS=y
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]48CONFIG_REGMAP=y
49CONFIG_SPL_REGMAP=y
50CONFIG_TPL_REGMAP=y
51CONFIG_SYSCON=y
52CONFIG_SPL_SYSCON=y
53CONFIG_TPL_SYSCON=y
54CONFIG_CLK=y
55CONFIG_SPL_CLK=y
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]56CONFIG_ROCKCHIP_GPIO=y
57CONFIG_SYS_I2C_ROCKCHIP=y
58CONFIG_MMC_DW=y
59CONFIG_MMC_DW_ROCKCHIP=y
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]60CONFIG_PHY_REALTEK=y
Jonas Karlman4ac67eb2024-02-17 00:22:30 +0000[diff] [blame]61CONFIG_DM_ETH_PHY=y
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]62CONFIG_PHY_GIGE=y
63CONFIG_ETH_DESIGNWARE=y
64CONFIG_GMAC_ROCKCHIP=y
Jagan Tekibf0e1342023-06-06 22:39:18 +0530[diff] [blame]65CONFIG_PHY_ROCKCHIP_INNO_USB2=y
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]66CONFIG_PINCTRL=y
67CONFIG_SPL_PINCTRL=y
68CONFIG_DM_PMIC=y
69CONFIG_PMIC_RK8XX=y
70CONFIG_SPL_DM_REGULATOR=y
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]71CONFIG_DM_REGULATOR_FIXED=y
72CONFIG_SPL_DM_REGULATOR_FIXED=y
73CONFIG_DM_REGULATOR_GPIO=y
74CONFIG_REGULATOR_RK8XX=y
75CONFIG_PWM_ROCKCHIP=y
76CONFIG_RAM=y
77CONFIG_SPL_RAM=y
78CONFIG_TPL_RAM=y
Jonas Karlman4ac67eb2024-02-17 00:22:30 +0000[diff] [blame]79CONFIG_DM_RNG=y
80CONFIG_RNG_ROCKCHIP=y
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]81CONFIG_BAUDRATE=1500000
82CONFIG_DEBUG_UART_SHIFT=2
Tom Rinidc172ee2022-12-04 09:39:03 -0500[diff] [blame]83CONFIG_SYS_NS16550_MEM32=y
Tom Rini4c66e9a2020-11-09 14:23:01 -0500[diff] [blame]84CONFIG_SYSINFO=y
85CONFIG_SYSINFO_SMBIOS=y
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]86CONFIG_SYSRESET=y
87# CONFIG_TPL_SYSRESET is not set
88CONFIG_USB=y
89CONFIG_USB_XHCI_HCD=y
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]90CONFIG_USB_EHCI_HCD=y
91CONFIG_USB_EHCI_GENERIC=y
92CONFIG_USB_OHCI_HCD=y
93CONFIG_USB_OHCI_GENERIC=y
94CONFIG_USB_DWC2=y
95CONFIG_USB_DWC3=y
Jagan Teki94e59a12023-06-06 22:39:15 +0530[diff] [blame]96CONFIG_USB_DWC3_GENERIC=y
Chen-Yu Tsai3aa5f1d2020-04-27 14:52:53 +0800[diff] [blame]97CONFIG_SPL_TINY_MEMSET=y
98CONFIG_TPL_TINY_MEMSET=y
99CONFIG_ERRNO_STR=y