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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Andre Przywara48321ba2016-05-31 10:45:06 -07002/*
3 * Configuration settings for the Allwinner A64 (sun50i) CPU
Andre Przywara48321ba2016-05-31 10:45:06 -07004 */
5
Andre Przywarae42015b2022-07-03 00:14:24 +01006#include <asm/arch/cpu.h>
7
Andre Przywara46c3d992017-01-02 11:48:36 +00008#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD)
Andre Przywara48321ba2016-05-31 10:45:06 -07009/* reserve space for BOOT0 header information */
Andre Przywaraf66cee32017-01-02 11:48:34 +000010 b reset
Andre Przywara48321ba2016-05-31 10:45:06 -070011 .space 1532
Andre Przywara46c3d992017-01-02 11:48:36 +000012#elif defined(CONFIG_ARM_BOOT_HOOK_RMR)
13/*
14 * Switch into AArch64 if needed.
15 * Refer to arch/arm/mach-sunxi/rmr_switch.S for the original source.
16 */
17 tst x0, x0 // this is "b #0x84" in ARM
18 b reset
19 .space 0x7c
Andre Przywarabbf99422016-08-23 22:19:30 +010020
Andre Przywara710c7a22023-04-05 21:30:11 +010021 .word 0xe28f0070 // add r0, pc, #112 // @(fel_stash - .)
22 .word 0xe59f106c // ldr r1, [pc, #108] // fel_stash - .
Andre Przywarabbf99422016-08-23 22:19:30 +010023 .word 0xe0800001 // add r0, r0, r1
24 .word 0xe580d000 // str sp, [r0]
25 .word 0xe580e004 // str lr, [r0, #4]
26 .word 0xe10fe000 // mrs lr, CPSR
27 .word 0xe580e008 // str lr, [r0, #8]
28 .word 0xee11ef10 // mrc 15, 0, lr, cr1, cr0, {0}
29 .word 0xe580e00c // str lr, [r0, #12]
30 .word 0xee1cef10 // mrc 15, 0, lr, cr12, cr0, {0}
31 .word 0xe580e010 // str lr, [r0, #16]
32
Andre Przywara710c7a22023-04-05 21:30:11 +010033 .word 0xe59f1034 // ldr r1, [pc, #52] ; RVBAR_ADDRESS
34 .word 0xe59f0034 // ldr r0, [pc, #52] ; SUNXI_SRAMC_BASE
35 .word 0xe5900024 // ldr r0, [r0, #36] ; SRAM_VER_REG
36 .word 0xe21000ff // ands r0, r0, #255 ; 0xff
37 .word 0x159f102c // ldrne r1, [pc, #44] ; RVBAR_ALTERNATIVE
38 .word 0xe59f002c // ldr r0, [pc, #44] ; CONFIG_*TEXT_BASE
Andre Przywara46c3d992017-01-02 11:48:36 +000039 .word 0xe5810000 // str r0, [r1]
40 .word 0xf57ff04f // dsb sy
41 .word 0xf57ff06f // isb sy
42 .word 0xee1c0f50 // mrc 15, 0, r0, cr12, cr0, {2} ; RMR
43 .word 0xe3800003 // orr r0, r0, #3
44 .word 0xee0c0f50 // mcr 15, 0, r0, cr12, cr0, {2} ; RMR
45 .word 0xf57ff06f // isb sy
46 .word 0xe320f003 // wfi
47 .word 0xeafffffd // b @wfi
Andre Przywara0b5e4282022-12-08 20:33:57 +000048
49 .word CONFIG_SUNXI_RVBAR_ADDRESS // writable RVBAR mapping addr
Andre Przywara710c7a22023-04-05 21:30:11 +010050 .word SUNXI_SRAMC_BASE
51 .word CONFIG_SUNXI_RVBAR_ALTERNATIVE // address for die variant
Andre Przywara46c3d992017-01-02 11:48:36 +000052#ifdef CONFIG_SPL_BUILD
53 .word CONFIG_SPL_TEXT_BASE
54#else
Simon Glass72cc5382022-10-20 18:22:39 -060055 .word CONFIG_TEXT_BASE
Andre Przywara46c3d992017-01-02 11:48:36 +000056#endif
Andre Przywarabbf99422016-08-23 22:19:30 +010057 .word fel_stash - .
Andre Przywara46c3d992017-01-02 11:48:36 +000058#else
59/* normal execution */
60 b reset
61#endif