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git01.mediatek.com / filogic / uboot / 4f809885dec59bb89dddc61f793edcbc2b8742ae / . / arch / arm / include / asm / arch-rockchip / cru_rk322x.h
blob: ee12fa831f28fb4899c2606822400194e53c56fd [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Kever Yangc5ccc322017-06-23 17:17:49 +0800[diff] [blame]2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
Kever Yangc5ccc322017-06-23 17:17:49 +0800[diff] [blame]4 */
5#ifndef _ASM_ARCH_CRU_RK322X_H
6#define _ASM_ARCH_CRU_RK322X_H
7
Kever Yangc5ccc322017-06-23 17:17:49 +0800[diff] [blame]8#define MHz 1000000
9#define OSC_HZ (24 * MHz)
10
11#define APLL_HZ (600 * MHz)
12#define GPLL_HZ (594 * MHz)
13
14#define CORE_PERI_HZ 150000000
15#define CORE_ACLK_HZ 300000000
16
17#define BUS_ACLK_HZ 148500000
18#define BUS_HCLK_HZ 148500000
19#define BUS_PCLK_HZ 74250000
20
21#define PERI_ACLK_HZ 148500000
22#define PERI_HCLK_HZ 148500000
23#define PERI_PCLK_HZ 74250000
24
25/* Private data for the clock driver - used by rockchip_get_cru() */
26struct rk322x_clk_priv {
27 struct rk322x_cru *cru;
28 ulong rate;
29};
30
31struct rk322x_cru {
32 struct rk322x_pll {
33 unsigned int con0;
34 unsigned int con1;
35 unsigned int con2;
36 } pll[4];
37 unsigned int reserved0[4];
38 unsigned int cru_mode_con;
39 unsigned int cru_clksel_con[35];
40 unsigned int cru_clkgate_con[16];
41 unsigned int cru_softrst_con[9];
42 unsigned int cru_misc_con;
43 unsigned int reserved1[2];
44 unsigned int cru_glb_cnt_th;
45 unsigned int reserved2[3];
46 unsigned int cru_glb_rst_st;
47 unsigned int reserved3[(0x1c0 - 0x150) / 4 - 1];
48 unsigned int cru_sdmmc_con[2];
49 unsigned int cru_sdio_con[2];
50 unsigned int reserved4[2];
51 unsigned int cru_emmc_con[2];
52 unsigned int reserved5[4];
53 unsigned int cru_glb_srst_fst_value;
54 unsigned int cru_glb_srst_snd_value;
55 unsigned int cru_pll_mask_con;
56};
57check_member(rk322x_cru, cru_pll_mask_con, 0x01f8);
58
59struct pll_div {
60 u32 refdiv;
61 u32 fbdiv;
62 u32 postdiv1;
63 u32 postdiv2;
64 u32 frac;
65};
66
67enum {
68 /* PLLCON0*/
69 PLL_BP_SHIFT = 15,
70 PLL_POSTDIV1_SHIFT = 12,
71 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
72 PLL_FBDIV_SHIFT = 0,
73 PLL_FBDIV_MASK = 0xfff,
74
75 /* PLLCON1 */
76 PLL_RST_SHIFT = 14,
77 PLL_PD_SHIFT = 13,
78 PLL_PD_MASK = 1 << PLL_PD_SHIFT,
79 PLL_DSMPD_SHIFT = 12,
80 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
81 PLL_LOCK_STATUS_SHIFT = 10,
82 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
83 PLL_POSTDIV2_SHIFT = 6,
84 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
85 PLL_REFDIV_SHIFT = 0,
86 PLL_REFDIV_MASK = 0x3f,
87
88 /* CRU_MODE */
89 GPLL_MODE_SHIFT = 12,
90 GPLL_MODE_MASK = 1 << GPLL_MODE_SHIFT,
91 GPLL_MODE_SLOW = 0,
92 GPLL_MODE_NORM,
93 CPLL_MODE_SHIFT = 8,
94 CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT,
95 CPLL_MODE_SLOW = 0,
96 CPLL_MODE_NORM,
97 DPLL_MODE_SHIFT = 4,
98 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT,
99 DPLL_MODE_SLOW = 0,
100 DPLL_MODE_NORM,
101 APLL_MODE_SHIFT = 0,
102 APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
103 APLL_MODE_SLOW = 0,
104 APLL_MODE_NORM,
105
106 /* CRU_CLK_SEL0_CON */
107 BUS_ACLK_PLL_SEL_SHIFT = 13,
108 BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT,
109 BUS_ACLK_PLL_SEL_APLL = 0,
110 BUS_ACLK_PLL_SEL_GPLL,
111 BUS_ACLK_PLL_SEL_HDMIPLL,
112 BUS_ACLK_DIV_SHIFT = 8,
113 BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
114 CORE_CLK_PLL_SEL_SHIFT = 6,
115 CORE_CLK_PLL_SEL_MASK = 3 << CORE_CLK_PLL_SEL_SHIFT,
116 CORE_CLK_PLL_SEL_APLL = 0,
117 CORE_CLK_PLL_SEL_GPLL,
118 CORE_CLK_PLL_SEL_DPLL,
119 CORE_DIV_CON_SHIFT = 0,
120 CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT,
121
122 /* CRU_CLK_SEL1_CON */
123 BUS_PCLK_DIV_SHIFT = 12,
124 BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT,
125 BUS_HCLK_DIV_SHIFT = 8,
126 BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT,
127 CORE_ACLK_DIV_SHIFT = 4,
128 CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT,
129 CORE_PERI_DIV_SHIFT = 0,
130 CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT,
131
132 /* CRU_CLKSEL5_CON */
133 GMAC_OUT_PLL_SHIFT = 15,
134 GMAC_OUT_PLL_MASK = 1 << GMAC_OUT_PLL_SHIFT,
135 GMAC_OUT_DIV_SHIFT = 8,
136 GMAC_OUT_DIV_MASK = 0x1f << GMAC_OUT_DIV_SHIFT,
137 MAC_PLL_SEL_SHIFT = 7,
138 MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT,
139 RMII_EXTCLK_SLE_SHIFT = 5,
140 RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SLE_SHIFT,
141 RMII_EXTCLK_SEL_INT = 0,
142 RMII_EXTCLK_SEL_EXT,
143 CLK_MAC_DIV_SHIFT = 0,
144 CLK_MAC_DIV_MASK = 0x1f << CLK_MAC_DIV_SHIFT,
145
146 /* CRU_CLKSEL10_CON */
147 PERI_PCLK_DIV_SHIFT = 12,
148 PERI_PCLK_DIV_MASK = 7 << PERI_PCLK_DIV_SHIFT,
149 PERI_PLL_SEL_SHIFT = 10,
150 PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT,
151 PERI_PLL_CPLL = 0,
152 PERI_PLL_GPLL,
153 PERI_PLL_HDMIPLL,
154 PERI_HCLK_DIV_SHIFT = 8,
155 PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
156 PERI_ACLK_DIV_SHIFT = 0,
157 PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
158
159 /* CRU_CLKSEL11_CON */
160 EMMC_PLL_SHIFT = 12,
161 EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
Kever Yangea141092017-08-03 20:07:45 +0800[diff] [blame]162 EMMC_SEL_CPLL = 0,
Kever Yangc5ccc322017-06-23 17:17:49 +0800[diff] [blame]163 EMMC_SEL_GPLL,
164 EMMC_SEL_24M,
165 SDIO_PLL_SHIFT = 10,
166 SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT,
Kever Yangea141092017-08-03 20:07:45 +0800[diff] [blame]167 SDIO_SEL_CPLL = 0,
Kever Yangc5ccc322017-06-23 17:17:49 +0800[diff] [blame]168 SDIO_SEL_GPLL,
169 SDIO_SEL_24M,
170 MMC0_PLL_SHIFT = 8,
171 MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
Kever Yangea141092017-08-03 20:07:45 +0800[diff] [blame]172 MMC0_SEL_CPLL = 0,
Kever Yangc5ccc322017-06-23 17:17:49 +0800[diff] [blame]173 MMC0_SEL_GPLL,
174 MMC0_SEL_24M,
175 MMC0_DIV_SHIFT = 0,
176 MMC0_DIV_MASK = 0xff << MMC0_DIV_SHIFT,
177
178 /* CRU_CLKSEL12_CON */
179 EMMC_DIV_SHIFT = 8,
180 EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT,
181 SDIO_DIV_SHIFT = 0,
182 SDIO_DIV_MASK = 0xff << SDIO_DIV_SHIFT,
183
184 /* CRU_CLKSEL26_CON */
185 DDR_CLK_PLL_SEL_SHIFT = 8,
186 DDR_CLK_PLL_SEL_MASK = 3 << DDR_CLK_PLL_SEL_SHIFT,
187 DDR_CLK_SEL_DPLL = 0,
188 DDR_CLK_SEL_GPLL,
189 DDR_CLK_SEL_APLL,
190 DDR_DIV_SEL_SHIFT = 0,
191 DDR_DIV_SEL_MASK = 3 << DDR_DIV_SEL_SHIFT,
192
193 /* CRU_CLKSEL27_CON */
194 VOP_DCLK_DIV_SHIFT = 8,
195 VOP_DCLK_DIV_MASK = 0xff << VOP_DCLK_DIV_SHIFT,
196 VOP_PLL_SEL_SHIFT = 1,
197 VOP_PLL_SEL_MASK = 1 << VOP_PLL_SEL_SHIFT,
198
199 /* CRU_CLKSEL29_CON */
200 GMAC_CLK_SRC_SHIFT = 12,
201 GMAC_CLK_SRC_MASK = 1 << GMAC_CLK_SRC_SHIFT,
202
203 /* CRU_SOFTRST5_CON */
204 DDRCTRL_PSRST_SHIFT = 11,
205 DDRCTRL_SRST_SHIFT = 10,
206 DDRPHY_PSRST_SHIFT = 9,
207 DDRPHY_SRST_SHIFT = 8,
208};
209#endif