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git01.mediatek.com / filogic / uboot / 4f5872770a065964efc305d3989f9ce4bc49cf58 / . / board / intel / cherryhill / cherryhill.c
blob: c037d5b14cd71c10ca58079b1463acb08f9794f7 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Bin Meng4ba75702017-08-15 22:42:02 -0700[diff] [blame]2/*
3 * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
Bin Meng4ba75702017-08-15 22:42:02 -0700[diff] [blame]4 */
5
6#include <common.h>
7#include <asm/arch/gpio.h>
Simon Glass6c34fc12019-09-25 08:00:11 -0600[diff] [blame]8#include <asm/fsp1/fsp_support.h>
Bin Meng4ba75702017-08-15 22:42:02 -0700[diff] [blame]9
10static const struct gpio_family gpio_family[] = {
11 GPIO_FAMILY_CONF("SOUTHEAST_2_hshvfamily_2x3_rcomp_7_0", NA, 0,
12 VOLT_1_8, NA, NA, NA, 0, ENABLE, 2, SOUTHEAST),
13
14 /* end of the table */
15 GPIO_FAMILY_CONF("GPIO FAMILY TABLE END", NA, 0,
16 VOLT_1_8, NA, NA, NA, 0, DISABLE, 0, TERMINATOR),
17};
18
19static const struct gpio_pad gpio_pad[] = {
20 GPIO_PAD_CONF("N37: CX_PRDY_B", NATIVE, M1, NA, NA, NA,
21 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
22 NA, 29, NA, 0x4c38, NORTH),
23 GPIO_PAD_CONF("N35: CX_PRDY_B_2", NATIVE, M1, NA, NA, NA,
24 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
25 NA, 27, NA, 0x4c28, NORTH),
26 GPIO_PAD_CONF("N39: CX_PREQ_B", NATIVE, M1, NA, NA, NA,
27 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
28 NA, 20, NA, 0x4858, NORTH),
29 GPIO_PAD_CONF("N48: GP_CAMERASB00", GPIO, M1, GPO, LOW,
30 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
31 NA, 37, NA, 0x5018, NORTH),
32 GPIO_PAD_CONF("N53: GP_CAMERASB01", GPIO, M1, GPO, LOW,
33 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
34 NA, 42, NA, 0x5040, NORTH),
35 GPIO_PAD_CONF("N46: GP_CAMERASB02", GPIO, M1, GPO, LOW,
36 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
37 NA, 35, NA, 0x5008, NORTH),
38 GPIO_PAD_CONF("N51: GP_CAMERASB03", GPIO, M1, GPO, LOW,
39 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
40 NA, 40, NA, 0x5030, NORTH),
41 GPIO_PAD_CONF("N56: GP_CAMERASB04", GPIO, M1, GPO, LOW,
42 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
43 NA, 45, NA, 0x5058, NORTH),
44 GPIO_PAD_CONF("N45: GP_CAMERASB05", GPIO, M1, GPO, LOW,
45 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
46 NA, 34, NA, 0x5000, NORTH),
47 GPIO_PAD_CONF("N49: GP_CAMERASB06", GPIO, M1, GPO, LOW,
48 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
49 NA, 38, NA, 0x5020, NORTH),
50 GPIO_PAD_CONF("N54: GP_CAMERASB07", GPIO, M1, GPO, LOW,
51 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
52 NA, 43, NA, 0x5048, NORTH),
53 GPIO_PAD_CONF("N47: GP_CAMERASB08", GPIO, M1, GPO, LOW,
54 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
55 NA, 36, NA, 0x5010, NORTH),
56 GPIO_PAD_CONF("N52: GP_CAMERASB09", GPIO, M1, GPO, LOW,
57 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
58 NA, 41, NA, 0x5038, NORTH),
59 GPIO_PAD_CONF("N50: GP_CAMERASB10", GPIO, M1, GPO, LOW,
60 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
61 NA, 39, NA, 0x5028, NORTH),
62 GPIO_PAD_CONF("N55: GP_CAMERASB11", GPIO, M1, GPO, LOW,
63 NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
64 NA, 44, NA, 0x5050, NORTH),
65 GPIO_PAD_CONF("N00: GPIO_DFX0", NATIVE, M5, NA, NA, NA,
66 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
67 NA, 0, NA, 0x4400, NORTH),
68 GPIO_PAD_CONF("N03: GPIO_DFX1", NATIVE, M5, NA, NA, NA,
69 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
70 NA, 3, NA, 0x4418, NORTH),
71 GPIO_PAD_CONF("N07: GPIO_DFX2", NATIVE, M5, NA, NA, NA,
72 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
73 NA, 2, NA, 0x4438, NORTH),
74 GPIO_PAD_CONF("N01: GPIO_DFX3", NATIVE, M5, NA, NA, NA,
75 NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
76 NA, 1, NA, 0x4408, NORTH),
77 GPIO_PAD_CONF("N05: GPIO_DFX4", GPIO, M1, GPO, HIGH, NA,
78 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
79 NA, 5, NA, 0x4428, NORTH),
80 GPIO_PAD_CONF("N04: GPIO_DFX5", GPIO, M1, GPO, HIGH, NA,
81 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
82 NA, 4, NA, 0x4420, NORTH),
83 GPIO_PAD_CONF("N08: GPIO_DFX6", NATIVE, M8, NA, NA, NA,
84 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
85 NA, 8, NA, 0x4440, NORTH),
86 GPIO_PAD_CONF("N02: GPIO_DFX7", GPIO, M1, GPO, LOW, NA,
87 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
88 NA, 2, NA, 0x4410, NORTH),
89 GPIO_PAD_CONF("N15: GPIO_SUS0", GPIO, M1, GPI, NA, NA,
90 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
91 NA, 9 , NA, 0x4800, NORTH),
92 GPIO_PAD_CONF("N19: GPIO_SUS1", GPIO, M1, GPI, NA, NA,
93 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
94 NA, 13, NA, 0x4820, NORTH),
95 GPIO_PAD_CONF("N24: GPIO_SUS2", GPIO, M1, GPI, NA, NA,
96 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
97 NA, 18, NA, 0x4848, NORTH),
98 GPIO_PAD_CONF("N17: GPIO_SUS3", NATIVE, M6, NA, NA, NA,
99 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
100 NA, 11, NA, 0x4810, NORTH),
101 GPIO_PAD_CONF("N22: GPIO_SUS4", GPIO, M1, GPO, HIGH, NA,
102 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
103 NA, 16, NA, 0x4838, NORTH),
104 GPIO_PAD_CONF("N20: GPIO_SUS5", GPIO, M1, GPO, HIGH, NA,
105 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
106 NA, 14, NA, 0x4828, NORTH),
107 GPIO_PAD_CONF("N25: GPIO_SUS6", GPIO, M1, GPI, NA, NA,
108 TRIG_EDGE_LOW, L9, NA, NA, NA, NON_MASKABLE,
109 EN_EDGE_RX_DATA, NO_INVERSION,
110 NA, 19, SCI, 0x4850, NORTH),
111 GPIO_PAD_CONF("N18: GPIO_SUS7", GPIO, M1, GPI, NA, NA,
112 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
113 NA, 12, SMI, 0x4818, NORTH),
114 GPIO_PAD_CONF("N71: HV_DDI0_DDC_SCL", NATIVE, M1, NA, NA, NA,
115 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
116 NA, 57, NA, 0x5458, NORTH),
117 GPIO_PAD_CONF("N66: HV_DDI0_DDC_SDA", NATIVE, M1, NA, NA, NA,
118 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
119 NA, 52, NA, 0x5430, NORTH),
120 GPIO_PAD_CONF("N61: HV_DDI0_HPD", NATIVE, M1, NA, NA, NA,
121 NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
122 NA, 47, NA, 0x5408, NORTH),
123 GPIO_PAD_CONF("N64: HV_DDI1_HPD", NATIVE, M1, NA, NA, NA,
124 NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
125 NA, 50, NA, 0x5420, NORTH),
126 GPIO_PAD_CONF("N67: HV_DDI2_DDC_SCL", NATIVE, M3, NA, NA, NA,
127 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
128 NA, 53, NA, 0x5438, NORTH),
129 GPIO_PAD_CONF("N62: HV_DDI2_DDC_SDA", NATIVE, M3, NA, NA, NA,
130 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
131 NA, 48, NA, 0x5410, NORTH),
132 GPIO_PAD_CONF("N68: HV_DDI2_HPD", NATIVE, M1, NA, NA, NA,
133 NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
134 NA, 54, NA, 0x5440, NORTH),
135 GPIO_PAD_CONF("N65: PANEL0_BKLTCTL", GPIO, M1, GPI, NA, NA,
136 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
137 NA, 51, NA, 0x5428, NORTH),
138 GPIO_PAD_CONF("N60: PANEL0_BKLTEN", GPIO, M1, GPI, NA, NA,
139 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
140 NA, 46, NA, 0x5400, NORTH),
141 GPIO_PAD_CONF("N72: PANEL0_VDDEN", GPIO, M1, GPI, NA, NA,
142 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
143 NA, 58, NA, 0x5460, NORTH),
144 GPIO_PAD_CONF("N63: PANEL1_BKLTCTL", NATIVE, M1, NA, NA, NA,
145 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
146 NA, 49, NA, 0x5418, NORTH),
147 GPIO_PAD_CONF("N70: PANEL1_BKLTEN", NATIVE, M1, NA, NA, NA,
148 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
149 NA, 56, NA, 0x5450, NORTH),
150 GPIO_PAD_CONF("N69: PANEL1_VDDEN", NATIVE, M1, NA, NA, NA,
151 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
152 NA, 55, NA, 0x5448, NORTH),
153 GPIO_PAD_CONF("N32: PROCHOT_B", NATIVE, M1, NA, NA, NA,
154 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
155 NA, 24, NA, 0x4c10, NORTH),
156 GPIO_PAD_CONF("N16: SEC_GPIO_SUS10", GPIO, M1, GPI, NA, NA,
157 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
158 NA, 10, NA, 0x4808, NORTH),
159 GPIO_PAD_CONF("N21: SEC_GPIO_SUS11", GPIO, M1, GPI, NA, NA,
160 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
161 NA, 15, NA, 0x4830, NORTH),
162 GPIO_PAD_CONF("N23: SEC_GPIO_SUS8", GPIO, M1, GPI, NA, NA,
163 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
164 NA, 17, NA, 0x4840, NORTH),
165 GPIO_PAD_CONF("N27: SEC_GPIO_SUS9", GPIO, M1, GPI, LOW, NA,
166 TRIG_LEVEL, L15, NA, NA, NA, NON_MASKABLE,
167 EN_RX_DATA, INV_RX_DATA,
168 NA, 21, SCI, 0x4860, NORTH),
169 GPIO_PAD_CONF("N31: TCK", NATIVE, M1, NA, NA, NA,
170 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
171 NA, 23, NA, 0x4c08, NORTH),
172 GPIO_PAD_CONF("N41: TDI", NATIVE, M1, NA, NA, NA,
173 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
174 NA, 33, NA, 0x4c58, NORTH),
175 GPIO_PAD_CONF("N39: TDO", NATIVE, M1, NA, NA, NA,
176 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
177 NA, 31, NA, 0x4c48, NORTH),
178 GPIO_PAD_CONF("N36: TDO_2", NATIVE, M1, NA, NA, NA,
179 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
180 NA, 28, NA, 0x4c30, NORTH),
181 GPIO_PAD_CONF("N34: TMS", NATIVE, M1, NA, NA, NA,
182 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
183 NA, 26, NA, 0x4c20, NORTH),
184 GPIO_PAD_CONF("N30: TRST_B", NATIVE, M1, NA, NA, NA,
185 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
186 NA, 22, NA, 0x4c00, NORTH),
187
188 GPIO_PAD_CONF("E21: MF_ISH_GPIO_0", GPIO, M1, GPI, NA, NA,
189 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
190 NA, 18, NA, 0x4830, EAST),
191 GPIO_PAD_CONF("E18: MF_ISH_GPIO_1", GPIO, M1, GPI, NA, NA,
192 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
193 NA, 15, NA, 0x4818, EAST),
194 GPIO_PAD_CONF("E24: MF_ISH_GPIO_2", GPIO, M1, GPI, NA, NA,
195 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
196 NA, 21, NA, 0x4848, EAST),
197 GPIO_PAD_CONF("E15: MF_ISH_GPIO_3", GPIO, M1, GPI, NA, NA,
198 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
199 NA, 12, NA, 0x4800, EAST),
200 GPIO_PAD_CONF("E22: MF_ISH_GPIO_4", GPIO, M1, GPI, NA, NA,
201 NA, L0, NA, NA, NA, NON_MASKABLE, NA, NO_INVERSION,
202 NA, 19, NA, 0x4838, EAST),
203 GPIO_PAD_CONF("E19: MF_ISH_GPIO_5", GPIO, M1, GPO, HIGH, NA,
204 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
205 NA, 16, NA, 0x4820, EAST),
206 GPIO_PAD_CONF("E25: MF_ISH_GPIO_6", NATIVE, M1, NA, NA, NA,
207 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
208 NA, 22, NA, 0x4850, EAST),
209 GPIO_PAD_CONF("E16: MF_ISH_GPIO_7", GPIO, M1, GPO, HIGH, NA,
210 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
211 NA, 13, NA, 0x4808, EAST),
212 GPIO_PAD_CONF("E23: MF_ISH_GPIO_8", NATIVE, M1, NA, NA, NA,
213 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
214 NA, 20, NA, 0x4840, EAST),
215 GPIO_PAD_CONF("E20: MF_ISH_GPIO_9", NATIVE, M1, NA, NA, NA,
216 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
217 NA, 17, NA, 0x4828, EAST),
218 GPIO_PAD_CONF("E26: MF_ISH_I2C1_SDA", NATIVE, M1, NA, NA, NA,
219 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
220 NA, 23, NA, 0x4858, EAST),
221 GPIO_PAD_CONF("E17: MF_ISH_I2C1_SCL", NATIVE, M1, NA, NA, NA,
222 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
223 NA, 14, NA, 0x4810, EAST),
224 GPIO_PAD_CONF("E04: PMU_AC_PRESENT", NATIVE, M1, NA, NA, NA,
225 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
226 NA, 4, NA, 0x4420, EAST),
227 GPIO_PAD_CONF("E01: PMU_BATLOW_B", NATIVE, M1, NA, NA, NA,
228 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
229 NA, 1, NA, 0x4408, EAST),
230 GPIO_PAD_CONF("E05: PMU_PLTRST_B", NATIVE, M1, NA, NA, NA,
231 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
232 NA, 5, NA, 0x4428, EAST),
233 GPIO_PAD_CONF("E07: PMU_SLP_LAN_B", NATIVE, M1, NA, NA, NA,
234 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
235 NA, 7, NA, 0x4438, EAST),
236 GPIO_PAD_CONF("E03: PMU_SLP_S0IX_B", NATIVE, M1, NA, NA, NA,
237 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
238 NA, 3, NA, 0x4418, EAST),
239 GPIO_PAD_CONF("E00: PMU_SLP_S3_B", NATIVE, M1, NA, NA, NA,
240 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
241 NA, 0, NA, 0x4400, EAST),
242 GPIO_PAD_CONF("E09: PMU_SLP_S4_B", NATIVE, M1, NA, NA, NA,
243 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
244 NA, 9, NA, 0x4448, EAST),
245 GPIO_PAD_CONF("E06: PMU_SUSCLK", NATIVE, M1, NA, NA, NA,
246 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
247 NA, 6, NA, 0x4430, EAST),
248 GPIO_PAD_CONF("E10: PMU_WAKE_B", NATIVE, M1, NA, NA, NA,
249 NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,
250 NA, 10, NA, 0x4450, EAST),
251 GPIO_PAD_CONF("E11: PMU_WAKE_LAN_B", NATIVE, M1, NA, NA, NA,
252 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
253 NA, 11, NA, 0x4458, EAST),
254 GPIO_PAD_CONF("E02: SUS_STAT_B", NATIVE, M1, NA, NA, NA,
255 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
256 NA, 2, NA, 0x4410, EAST),
257
258 GPIO_PAD_CONF("SE16: SDMMC1_CLK", NATIVE, M1, NA, NA, HIGH,
259 NA, NA, P_20K_L, NA, NA, NA, NA, NO_INVERSION,
260 NA, 9, NA, 0x4808, SOUTHEAST),
261 GPIO_PAD_CONF("SE23: SDMMC1_CMD", NATIVE, M1, NA, NA, HIGH,
262 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
263 NA, 16, NA, 0x4840, SOUTHEAST),
264 GPIO_PAD_CONF("SE17: SDMMC1_D0", NATIVE, M1, NA, NA, HIGH,
265 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
266 NA, 10, NA, 0x4810, SOUTHEAST),
267 GPIO_PAD_CONF("SE24: SDMMC1_D1", NATIVE, M1, NA, NA, HIGH,
268 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
269 NA, 17, NA, 0x4848, SOUTHEAST),
270 GPIO_PAD_CONF("SE20: SDMMC1_D2", NATIVE, M1, NA, NA, HIGH,
271 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
272 NA, 13, NA, 0x4828, SOUTHEAST),
273 GPIO_PAD_CONF("SE26: SDMMC1_D3_CD_B", NATIVE, M1, NA, NA, HIGH,
274 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
275 NA, 19, NA, 0x4858, SOUTHEAST),
276 GPIO_PAD_CONF("SE67: MMC1_D4_SD_WE", NATIVE, M1, NA, NA, HIGH,
277 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
278 NA, 41, NA, 0x5438, SOUTHEAST),
279 GPIO_PAD_CONF("SE65: MMC1_D5", NATIVE, M1, NA, NA, HIGH,
280 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
281 NA, 39, NA, 0x5428, SOUTHEAST),
282 GPIO_PAD_CONF("SE63: MMC1_D6", NATIVE, M1, NA, NA, HIGH,
283 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
284 NA, 37, NA, 0x5418, SOUTHEAST),
285 GPIO_PAD_CONF("SE68: MMC1_D7", NATIVE, M1, NA, NA, HIGH,
286 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
287 NA, 42, NA, 0x5440, SOUTHEAST),
288 GPIO_PAD_CONF("SE69: MMC1_RCLK", NATIVE, M1, NA, NA, NA,
289 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
290 NA, 43, NA, 0x5448, SOUTHEAST),
291 GPIO_PAD_CONF("SE77: GPIO_ALERT", GPIO, M1, GPI, NA, NA,
292 TRIG_LEVEL, L2, NA, NA, NA, NON_MASKABLE,
293 EN_RX_DATA, INV_RX_DATA,
294 NA, 46, NA, 0x5810, SOUTHEAST),
295 GPIO_PAD_CONF("SE79: ILB_SERIRQ", NATIVE, M1, NA, NA, NA,
296 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
297 NA, 48, NA, 0x5820, SOUTHEAST),
298 GPIO_PAD_CONF("SE51: MF_LPC_CLKOUT0", NATIVE, M1, NA, NA, NA,
299 NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,
300 NA, 32, NA, 0x5030, SOUTHEAST),
301 GPIO_PAD_CONF("SE49: MF_LPC_CLKOUT1", NATIVE, M1, NA, NA, NA,
302 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
303 NA, 30, NA, 0x5020, SOUTHEAST),
304 GPIO_PAD_CONF("SE47: MF_LPC_AD0", NATIVE, M1, NA, NA, NA,
305 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
306 NA, 28, NA, 0x5010, SOUTHEAST),
307 GPIO_PAD_CONF("SE52: MF_LPC_AD1", NATIVE, M1, NA, NA, NA,
308 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
309 NA, 33, NA, 0x5038, SOUTHEAST),
310 GPIO_PAD_CONF("SE45: MF_LPC_AD2", NATIVE, M1, NA, NA, NA,
311 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
312 NA, 26, NA, 0x5000, SOUTHEAST),
313 GPIO_PAD_CONF("SE50: MF_LPC_AD3", NATIVE, M1, NA, NA, NA,
314 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
315 NA, 31, NA, 0x5028, SOUTHEAST),
316 GPIO_PAD_CONF("SE46: LPC_CLKRUNB", NATIVE, M1, NA, NA, NA,
317 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
318 NA, 27, NA, 0x5008, SOUTHEAST),
319 GPIO_PAD_CONF("SE48: LPC_FRAMEB", NATIVE, M1, NA, NA, NA,
320 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
321 NA, 29, NA, 0x5018, SOUTHEAST),
322 GPIO_PAD_CONF("SE00: MF_PLT_CLK0", NATIVE, M1, NA, NA, NA,
323 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
324 NA, 0, NA, 0x4400, SOUTHEAST),
325 GPIO_PAD_CONF("SE02: MF_PLT_CLK1", NATIVE, M1, NA, NA, NA,
326 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
327 NA, 1, NA, 0x4410, SOUTHEAST),
328 GPIO_PAD_CONF("SE07: MF_PLT_CLK2", GPIO, M1, GPI, NA, NA,
329 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
330 NA, 7, NA, 0x4438, SOUTHEAST),
331 GPIO_PAD_CONF("SE04: MF_PLT_CLK3", GPIO, M1, GPI, NA, NA,
332 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
333 NA, 4, NA, 0x4420, SOUTHEAST),
334 GPIO_PAD_CONF("SE03: MF_PLT_CLK4", GPIO, M1, GPO, LOW, NA,
335 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
336 NA, 3, NA, 0x4418, SOUTHEAST),
337 GPIO_PAD_CONF("SE06: MF_PLT_CLK5", GPIO, M3, GPO, LOW, NA,
338 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
339 NA, 6, NA, 0x4430, SOUTHEAST),
340 GPIO_PAD_CONF("SE83: SUSPWRDNACK", NATIVE, M1, NA, NA, NA,
341 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
342 NA, 52, NA, 0x5840, SOUTHEAST),
343 GPIO_PAD_CONF("SE05: PWM0", GPIO, M1, GPO, LOW, NA,
344 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
345 NA, 5, NA, 0x4428, SOUTHEAST),
346 GPIO_PAD_CONF("SE01: PWM1", GPIO, M1, GPO, HIGH, NA,
347 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
348 NA, 1, NA, 0x4408, SOUTHEAST),
349 GPIO_PAD_CONF("SE85: SDMMC3_1P8_EN", NATIVE, M1, NA, NA, NA,
350 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
351 NA, 54, NA, 0x5850, SOUTHEAST),
352 GPIO_PAD_CONF("SE81: SDMMC3_CD_B", NATIVE, M1, NA, NA, NA,
353 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
354 NA, 50, NA, 0x5830, SOUTHEAST),
355 GPIO_PAD_CONF("SE31: SDMMC3_CLK", NATIVE, M1, NA, NA, NA,
356 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
357 NA, 21, NA, 0x4c08, SOUTHEAST),
358 GPIO_PAD_CONF("SE34: SDMMC3_CMD", NATIVE, M1, NA, NA, NA,
359 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
360 NA, 24, NA, 0x4c20, SOUTHEAST),
361 GPIO_PAD_CONF("SE35: SDMMC3_D0", NATIVE, M1, NA, NA, NA,
362 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
363 NA, 25, NA, 0x4c28, SOUTHEAST),
364 GPIO_PAD_CONF("SE30: SDMMC3_D1", NATIVE, M1, NA, NA, NA,
365 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
366 NA, 20, NA, 0x4c00, SOUTHEAST),
367 GPIO_PAD_CONF("SE33: SDMMC3_D2", NATIVE, M1, NA, NA, NA,
368 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
369 NA, 23, NA, 0x4c18, SOUTHEAST),
370 GPIO_PAD_CONF("SE32: SDMMC3_D3", NATIVE, M1, NA, NA, NA,
371 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
372 NA, 22, NA, 0x4c10, SOUTHEAST),
373 GPIO_PAD_CONF("SE78: SDMMC3_PWR_EN_B", NATIVE, M1, NA, NA, NA,
374 NA, NA, P_20K_L, NA, NA, NA, NA, NO_INVERSION,
375 NA, 47, NA, 0x5818, SOUTHEAST),
376 GPIO_PAD_CONF("SE19: SDMMC2_CLK", NATIVE, M1, NA, NA, NA,
377 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
378 NA, 12, NA, 0x4820, SOUTHEAST),
379 GPIO_PAD_CONF("SE22: SDMMC2_CMD", NATIVE, M1, NA, NA, NA,
380 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
381 NA, 15, NA, 0x4838, SOUTHEAST),
382 GPIO_PAD_CONF("SE25: SDMMC2_D0", NATIVE, M1, NA, NA, NA,
383 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
384 NA, 18, NA, 0x4850, SOUTHEAST),
385 GPIO_PAD_CONF("SE18: SDMMC2_D1", NATIVE, M1, NA, NA, NA,
386 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
387 NA, 11, NA, 0x4818, SOUTHEAST),
388 GPIO_PAD_CONF("SE21: SDMMC2_D2", NATIVE, M1, NA, NA, NA,
389 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
390 NA, 14, NA, 0x4830, SOUTHEAST),
391 GPIO_PAD_CONF("SE15: SDMMC2_D3_CD_B", NATIVE, M1, NA, NA, NA,
392 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
393 NA, 8, NA, 0x4800, SOUTHEAST),
394 GPIO_PAD_CONF("SE62: SPI1_CLK", NATIVE, M1, NA, NA, NA,
395 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
396 NA, 36, NA, 0x5410, SOUTHEAST),
397 GPIO_PAD_CONF("SE61: SPI1_CS0_B", NATIVE, M1, NA, NA, NA,
398 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
399 NA, 35, NA, 0x5408, SOUTHEAST),
400 GPIO_PAD_CONF("SE66: SPI1_CS1_B", NATIVE, M1, NA, NA, NA,
401 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
402 NA, 40, NA, 0x5430, SOUTHEAST),
403 GPIO_PAD_CONF("SE60: SPI1_MISO", NATIVE, M1, NA, NA, NA,
404 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
405 NA, 34, NA, 0x5400, SOUTHEAST),
406 GPIO_PAD_CONF("SE64: SPI1_MOSI", NATIVE, M1, NA, NA, NA,
407 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
408 NA, 38, NA, 0x5420, SOUTHEAST),
409 GPIO_PAD_CONF("SE80: USB_OC0_B", NATIVE, M1, NA, NA, NA,
410 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
411 NA, 49, NA, 0x5828, SOUTHEAST),
412 GPIO_PAD_CONF("SE75: USB_OC1_B", NATIVE, M1, NA, NA, NA,
413 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
414 NA, 44, NA, 0x5800, SOUTHEAST),
415 GPIO_PAD_CONF("SW02: FST_SPI_CLK", NATIVE, M1, NA, NA, NA,
416 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
417 NA, 2, NA, 0x4410, SOUTHWEST),
418 GPIO_PAD_CONF("SW06: FST_SPI_CS0_B", NATIVE, M1, NA, NA, NA,
419 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
420 NA, 6, NA, 0x4430, SOUTHWEST),
421 GPIO_PAD_CONF("SW04: FST_SPI_CS1_B", GPIO, M1, GPO, HIGH, NA,
422 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
423 NA, 4, NA, 0x4420, SOUTHWEST),
424 GPIO_PAD_CONF("SW07: FST_SPI_CS2_B", GPIO, M1, GPO, LOW, NA,
425 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
426 NA, 7, NA, 0x4438, SOUTHWEST),
427 GPIO_PAD_CONF("SW01: FST_SPI_D0", NATIVE, M1, NA, NA, NA,
428 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
429 NA, 1, NA, 0x4408, SOUTHWEST),
430 GPIO_PAD_CONF("SW05: FST_SPI_D1", NATIVE, M1, NA, NA, NA,
431 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
432 NA, 5, NA, 0x4428, SOUTHWEST),
433 GPIO_PAD_CONF("SW00: FST_SPI_D2", NATIVE, M1, NA, NA, NA,
434 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
435 NA, 0, NA, 0x4400, SOUTHWEST),
436 GPIO_PAD_CONF("SW03: FST_SPI_D3", NATIVE, M1, NA, NA, NA,
437 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
438 NA, 3, NA, 0x4418, SOUTHWEST),
439 GPIO_PAD_CONF("SW30: MF_HDA_CLK", NATIVE, M2, NA, NA, NA,
440 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
441 NA, 16, NA, 0x4c00, SOUTHWEST),
442 GPIO_PAD_CONF("SW37: MF_HDA_DOCKENB", NATIVE, M1, NA, NA, NA,
443 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
444 NA, 23, NA, 0x4c38, SOUTHWEST),
445 GPIO_PAD_CONF("SW34: MF_HDA_DOCKRSTB", NATIVE, M1, NA, NA, NA,
446 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
447 NA, 20, NA, 0x4c20, SOUTHWEST),
448 GPIO_PAD_CONF("SW31: MF_HDA_RSTB", NATIVE, M2, NA, NA, NA,
449 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
450 NA, 17, NA, 0x4c08, SOUTHWEST),
451 GPIO_PAD_CONF("SW32: MF_HDA_SDI0", NATIVE, M2, NA, NA, NA,
452 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
453 NA, 18, NA, 0x4c10, SOUTHWEST),
454 GPIO_PAD_CONF("SW36: MF_HDA_SDI1", NATIVE, M2, NA, NA, NA,
455 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
456 NA, 22, NA, 0x4c30, SOUTHWEST),
457 GPIO_PAD_CONF("SW33: MF_HDA_SDO", NATIVE, M2, NA, NA, NA,
458 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
459 NA, 19, NA, 0x4c18, SOUTHWEST),
460 GPIO_PAD_CONF("SW35: MF_HDA_SYNC", NATIVE, M2, NA, NA, NA,
461 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
462 NA, 21, NA, 0x4c28, SOUTHWEST),
463 GPIO_PAD_CONF("SW18: UART1_CTS_B", NATIVE, M1, NA, NA, NA,
464 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
465 NA, 11, NA, 0x4818, SOUTHWEST),
466 GPIO_PAD_CONF("SW15: UART1_RTS_B", NATIVE, M1, NA, NA, NA,
467 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
468 NA, 8, NA, 0x4800, SOUTHWEST),
469 GPIO_PAD_CONF("SW16: UART1_RXD", NATIVE, M1, NA, NA, NA,
470 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
471 NA, 9, NA, 0x4808, SOUTHWEST),
472 GPIO_PAD_CONF("SW20: UART1_TXD", NATIVE, M1, NA, NA, NA,
473 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
474 NA, 13, NA, 0x4828, SOUTHWEST),
475 GPIO_PAD_CONF("SW22: UART2_CTS_B", NATIVE, M1, NA, NA, NA,
476 NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,
477 NA, 15, NA, 0x4838, SOUTHWEST),
478 GPIO_PAD_CONF("SW19: UART2_RTS_B", NATIVE, M1, NA, NA, NA,
479 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
480 NA, 12, NA, 0x4820, SOUTHWEST),
481 GPIO_PAD_CONF("SW17: UART2_RXD", NATIVE, M1, NA, NA, NA,
482 NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,
483 NA, 10, NA, 0x4810, SOUTHWEST),
484 GPIO_PAD_CONF("SW21: UART2_TXD", NATIVE, M1, NA, NA, NA,
485 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
486 NA, 14, NA, 0x4830, SOUTHWEST),
487 GPIO_PAD_CONF("SW50: I2C4_SCL", NATIVE, M3, NA, NA, NA,
488 NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,
489 NA, 29, NA, 0x5028, SOUTHWEST),
490 GPIO_PAD_CONF("SW46: I2C4_SDA", NATIVE, M3, NA, NA, NA,
491 NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,
492 NA, 25, NA, 0x5008, SOUTHWEST),
493 GPIO_PAD_CONF("SW49: I2C_NFC_SDA", NATIVE, M1, NA, NA, NA,
494 NA, NA, P_20K_H, NA, NA, NA, NA, INV_TX_ENABLE,
495 NA, 28, NA, 0x5020, SOUTHWEST),
496 GPIO_PAD_CONF("SW52: I2C_NFC_SCL", NATIVE, M1, NA, NA, NA,
497 NA, NA, P_20K_H, NA, NA, NA, NA, INV_TX_ENABLE,
498 NA, 31, NA, 0x5038, SOUTHWEST),
499 GPIO_PAD_CONF("SW77: GP_SSP_2_CLK", NATIVE, M1, NA, NA, NA,
500 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
501 NA, 50, NA, 0x5c10, SOUTHWEST),
502 GPIO_PAD_CONF("SW81: GP_SSP_2_FS", NATIVE, M1, NA, NA, NA,
503 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
504 NA, 54, NA, 0x5c30, SOUTHWEST),
505 GPIO_PAD_CONF("SW79: GP_SSP_2_RXD", NATIVE, M1, NA, NA, NA,
506 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
507 NA, 52, NA, 0x5c20, SOUTHWEST),
508 GPIO_PAD_CONF("SW82: GP_SSP_2_TXD", NATIVE, M1, NA, NA, NA,
509 NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
510 NA, 55, NA, 0x5C38, SOUTHWEST),
511 GPIO_PAD_CONF("SW90: PCIE_CLKREQ0B", NATIVE, M1, NA, NA, NA,
512 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
513 NA, 48, NA, 0x5c00, SOUTHWEST),
514 GPIO_PAD_CONF("SW91: PCIE_CLKREQ1B", NATIVE, M1, NA, NA, NA,
515 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
516 NA, 49, NA, 0x5c08, SOUTHWEST),
517 GPIO_PAD_CONF("SW93: PCIE_CLKREQ2B", NATIVE, M1, NA, NA, NA,
518 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
519 NA, 51, NA, 0x5c18, SOUTHWEST),
520 GPIO_PAD_CONF("SW95: PCIE_CLKREQ3B", NATIVE, M2, NA, NA, NA,
521 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
522 NA, 53, NA, 0x5c28, SOUTHWEST),
523 GPIO_PAD_CONF("SW75: SATA_GP0", GPIO, M1, GPO, HIGH, NA,
524 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
525 NA, 40, NA, 0x5800, SOUTHWEST),
526 GPIO_PAD_CONF("SW76: SATA_GP1", GPIO, M1, GPI, HIGH, NA,
527 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
528 NA, 41, NA, 0x5808, SOUTHWEST),
529 GPIO_PAD_CONF("SW78: SATA_GP2", NATIVE, M1, NA, NA, NA,
530 NA, NA, NA, ENABLE, NA, NA, NA, NO_INVERSION,
531 NA, 43, NA, 0x5818, SOUTHWEST),
532 GPIO_PAD_CONF("SW80: SATA_GP3", GPIO, M2, GPI, LOW, NA,
533 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
534 NA, 45, NA, 0x5828, SOUTHWEST),
535 GPIO_PAD_CONF("SW77: SATA_LEDN", NATIVE, M1, NA, NA, NA,
536 NA, NA, NA, ENABLE, NA, NA, NA, NO_INVERSION,
537 NA, 42, NA, 0x5810, SOUTHWEST),
538 GPIO_PAD_CONF("SW79: MF_SMB_ALERTB", NATIVE, M1, NA, NA,
539 NA, NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
540 NA, 44, NA, 0x5820, SOUTHWEST),
541 GPIO_PAD_CONF("SW81: MF_SMB_CLK", NATIVE, M1, NA, NA, NA,
542 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
543 NA, 46, NA, 0x5830, SOUTHWEST),
544 GPIO_PAD_CONF("SW82: MF_SMB_DATA", NATIVE, M1, NA, NA, NA,
545 NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
546 NA, 47, NA, 0x5838, SOUTHWEST),
547 GPIO_PAD_CONF("SW90: PCIE_CLKREQ0B", NATIVE, M1, NA, NA, NA,
548 NA, NA, NA, NA, NA, NA, NA, NA,
549 NA, 48, NA, 0x5c00, SOUTHWEST),
550 GPIO_PAD_CONF("SW91: PCIE_CLKREQ1B", NATIVE, M1, NA, NA, NA,
551 NA, NA, NA, NA, NA, NA, NA, NA,
552 NA, 49, NA, 0x5c08, SOUTHWEST),
553 GPIO_PAD_CONF("SW93: PCIE_CLKREQ2B", NATIVE, M1, NA, NA, NA,
554 NA, NA, NA, NA, NA, NA, NA, NA,
555 NA, 51, NA, 0x5c18, SOUTHWEST),
556 GPIO_PAD_CONF("SW95: PCIE_CLKREQ3B", NATIVE, M2, NA, NA, NA,
557 NA, NA, NA, NA, NA, NA, NA, NA,
558 NA, 53, NA, 0x5c28, SOUTHWEST),
559 GPIO_PAD_CONF("SW75: SATA_GP0", GPIO, M1, GPO, HIGH, NA, NA,
560 NA, NA, NA, NA, NA, NA, NA,
561 NA, 40, NA, 0x5800, SOUTHWEST),
562 GPIO_PAD_CONF("SW76: SATA_GP1", GPIO, M1, GPI, HIGH, NA, NA,
563 NA, NA, NA, NA, NA, NA, NA,
564 NA, 41, NA, 0x5808, SOUTHWEST),
565 GPIO_PAD_CONF("SW78: SATA_GP2", NATIVE, M1, NA, NA, NA,
566 NA, NA, NA, ENABLE, NA, NA, NA, NA,
567 NA, 43, NA, 0x5818, SOUTHWEST),
568 GPIO_PAD_CONF("SW80: SATA_GP3", GPIO, M2, GPI, LOW, NA,
569 NA, NA, NA, NA, NA, NA, NA, NA,
570 NA, 45, NA, 0x5828, SOUTHWEST),
571 GPIO_PAD_CONF("SW77: SATA_LEDN", NATIVE, M1, NA, NA, NA,
572 NA, NA, NA, ENABLE, NA, NA, NA, NA,
573 NA, 42, NA, 0x5810, SOUTHWEST),
574 GPIO_PAD_CONF("SW79: MF_SMB_ALERTB", NATIVE, M1, NA, NA,
575 NA, NA, NA, P_20K_H, NA, NA, NA, NA, NA,
576 NA, 44, NA, 0x5820, SOUTHWEST),
577 GPIO_PAD_CONF("SW81: MF_SMB_CLK", NATIVE, M1, NA, NA, NA,
578 NA, NA, P_20K_H, NA, NA, NA, NA, NA,
579 NA, 46, NA, 0x5830, SOUTHWEST),
580 GPIO_PAD_CONF("SW82: MF_SMB_DATA", NATIVE, M1, NA, NA, NA,
581 NA, NA, P_20K_H, NA, NA, NA, NA, NA,
582 NA, 47, NA, 0x5838, SOUTHWEST),
583
584 /* end of the table */
585 GPIO_PAD_CONF("GPIO PAD TABLE END", NATIVE, M1, NA, NA, NA,
586 NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
587 NA, 0, NA, 0, TERMINATOR),
588};
589
590void update_fsp_gpio_configs(const struct gpio_family **family,
591 const struct gpio_pad **pad)
592{
593 *family = gpio_family;
594 *pad = gpio_pad;
595}