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wdenkef3386f2004-10-10 21:27:30 +00001/*
2 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
3 * Scott McNutt <smcnutt@psyent.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkef3386f2004-10-10 21:27:30 +00006 */
7
8#ifndef __ASM_NIOS2_CACHE_H_
9#define __ASM_NIOS2_CACHE_H_
10
Anton Staaf4b170832011-10-17 16:46:05 -070011/*
Thomas Chou741085b2015-10-23 07:58:20 +080012 * Valid L1 data cache line sizes for the NIOS2 architecture are 4,
13 * 16, and 32 bytes. We default to the largest of these values for
14 * alignment of DMA buffers.
Anton Staaf4b170832011-10-17 16:46:05 -070015 */
Anton Staaf4b170832011-10-17 16:46:05 -070016#define ARCH_DMA_MINALIGN 32
Anton Staaf4b170832011-10-17 16:46:05 -070017
wdenkef3386f2004-10-10 21:27:30 +000018#endif /* __ASM_NIOS2_CACHE_H_ */