Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 1 | .. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
| 2 | .. sectionauthor:: Vignesh Raghavendra <vigneshr@ti.com> |
| 3 | |
Bryan Brattlof | 10d3f17 | 2022-12-19 14:29:49 -0600 | [diff] [blame] | 4 | AM62 Platforms |
| 5 | =============== |
Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 6 | |
| 7 | Introduction: |
| 8 | ------------- |
| 9 | The AM62 SoC family is the follow on AM335x built on the K3 Multicore |
| 10 | SoC architecture platform, providing ultra-low-power modes, dual |
| 11 | display, multi-sensor edge compute, security and other BOM-saving |
| 12 | integrations. The AM62 SoC targets a broad market to enable |
| 13 | applications such as Industrial HMI, PLC/CNC/Robot control, Medical |
| 14 | Equipment, Building Automation, Appliances and more. |
| 15 | |
| 16 | Some highlights of this SoC are: |
| 17 | |
| 18 | * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. |
| 19 | Pin-to-pin compatible options for single and quad core are available. |
| 20 | * Cortex-M4F for general-purpose or safety usage. |
| 21 | * Dual display support, providing 24-bit RBG parallel interface and |
| 22 | OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display |
| 23 | resolution. |
| 24 | * Selectable GPU support, up to 8GFLOPS, providing better user experience |
| 25 | in 3D graphic display case and Android. |
| 26 | * PRU(Programmable Realtime Unit) support for customized programmable |
| 27 | interfaces/IOs. |
| 28 | * Integrated Giga-bit Ethernet switch supporting up to a total of two |
| 29 | external ports (TSN capable). |
| 30 | * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for |
| 31 | NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, |
| 32 | 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. |
| 33 | * Dedicated Centralized System Controller for Security, Power, and |
| 34 | Resource Management. |
| 35 | * Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, |
| 36 | enabling battery powered system design. |
| 37 | |
| 38 | More details can be found in the Technical Reference Manual: |
| 39 | https://www.ti.com/lit/pdf/spruiv7 |
| 40 | |
Nishanth Menon | 4981d9a | 2023-07-27 13:59:00 -0500 | [diff] [blame] | 41 | Platform information: |
| 42 | |
| 43 | * https://www.ti.com/tool/SK-AM62B |
| 44 | |
Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 45 | Boot Flow: |
| 46 | ---------- |
| 47 | Below is the pictorial representation of boot flow: |
| 48 | |
Nishanth Menon | b47c9f7 | 2023-07-27 13:58:45 -0500 | [diff] [blame] | 49 | .. image:: img/boot_diagram_k3_current.svg |
Heinrich Schuchardt | bcd233b | 2023-08-22 11:40:57 -0500 | [diff] [blame] | 50 | :alt: Boot flow diagram |
Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 51 | |
| 52 | - Here TIFS acts as master and provides all the critical services. R5/A53 |
| 53 | requests TIFS to get these services done as shown in the above diagram. |
| 54 | |
| 55 | Sources: |
| 56 | -------- |
Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 57 | |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 58 | .. include:: ../ti/k3.rst |
Nishanth Menon | ee91e48 | 2023-07-27 13:58:44 -0500 | [diff] [blame] | 59 | :start-after: .. k3_rst_include_start_boot_sources |
| 60 | :end-before: .. k3_rst_include_end_boot_sources |
Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 61 | |
| 62 | Build procedure: |
| 63 | ---------------- |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 64 | 0. Setup the environment variables: |
Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 65 | |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 66 | .. include:: ../ti/k3.rst |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 67 | :start-after: .. k3_rst_include_start_common_env_vars_desc |
| 68 | :end-before: .. k3_rst_include_end_common_env_vars_desc |
Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 69 | |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 70 | .. include:: ../ti/k3.rst |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 71 | :start-after: .. k3_rst_include_start_board_env_vars_desc |
| 72 | :end-before: .. k3_rst_include_end_board_env_vars_desc |
Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 73 | |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 74 | Set the variables corresponding to this platform: |
Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 75 | |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 76 | .. include:: ../ti/k3.rst |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 77 | :start-after: .. k3_rst_include_start_common_env_vars_defn |
| 78 | :end-before: .. k3_rst_include_end_common_env_vars_defn |
Neha Malcom Francis | 507be12 | 2023-07-22 00:14:43 +0530 | [diff] [blame] | 79 | .. code-block:: bash |
Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 80 | |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 81 | $ export UBOOT_CFG_CORTEXR=am62x_evm_r5_defconfig |
| 82 | $ export UBOOT_CFG_CORTEXA=am62x_evm_a53_defconfig |
| 83 | $ export TFA_BOARD=lite |
| 84 | $ # we dont use any extra TFA parameters |
| 85 | $ unset TFA_EXTRA_ARGS |
| 86 | $ export OPTEE_PLATFORM=k3-am62x |
| 87 | $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y" |
Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 88 | |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 89 | .. am62x_evm_rst_include_start_build_steps |
Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 90 | |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 91 | 1. Trusted Firmware-A: |
Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 92 | |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 93 | .. include:: ../ti/k3.rst |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 94 | :start-after: .. k3_rst_include_start_build_steps_tfa |
| 95 | :end-before: .. k3_rst_include_end_build_steps_tfa |
Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 96 | |
Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 97 | |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 98 | 2. OP-TEE: |
Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 99 | |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 100 | .. include:: ../ti/k3.rst |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 101 | :start-after: .. k3_rst_include_start_build_steps_optee |
| 102 | :end-before: .. k3_rst_include_end_build_steps_optee |
| 103 | |
| 104 | 3. U-Boot: |
| 105 | |
Nishanth Menon | 4ef5f34 | 2023-08-22 11:41:02 -0500 | [diff] [blame^] | 106 | * 3.1 R5: |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 107 | |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 108 | .. include:: ../ti/k3.rst |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 109 | :start-after: .. k3_rst_include_start_build_steps_spl_r5 |
| 110 | :end-before: .. k3_rst_include_end_build_steps_spl_r5 |
| 111 | |
Nishanth Menon | 4ef5f34 | 2023-08-22 11:41:02 -0500 | [diff] [blame^] | 112 | * 3.2 A53: |
Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 113 | |
Marcel Ziswiler | 315deb3 | 2023-08-04 12:08:08 +0200 | [diff] [blame] | 114 | .. include:: ../ti/k3.rst |
Nishanth Menon | b7ee22f | 2023-07-27 13:58:48 -0500 | [diff] [blame] | 115 | :start-after: .. k3_rst_include_start_build_steps_uboot |
| 116 | :end-before: .. k3_rst_include_end_build_steps_uboot |
| 117 | .. am62x_evm_rst_include_end_build_steps |
Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 118 | |
| 119 | Target Images |
| 120 | -------------- |
Tom Rini | fdf4503 | 2023-07-25 12:44:16 -0400 | [diff] [blame] | 121 | In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC |
| 122 | variant (GP, HS-FS, HS-SE) requires a different source for these files. |
Neha Malcom Francis | 507be12 | 2023-07-22 00:14:43 +0530 | [diff] [blame] | 123 | |
| 124 | - GP |
| 125 | |
| 126 | * tiboot3-am62x-gp-evm.bin from step 3.1 |
| 127 | * tispl.bin_unsigned, u-boot.img_unsigned from step 3.2 |
| 128 | |
| 129 | - HS-FS |
| 130 | |
| 131 | * tiboot3-am62x-hs-fs-evm.bin from step 3.1 |
| 132 | * tispl.bin, u-boot.img from step 3.2 |
| 133 | |
| 134 | - HS-SE |
| 135 | |
| 136 | * tiboot3-am62x-hs-evm.bin from step 3.1 |
| 137 | * tispl.bin, u-boot.img from step 3.2 |
Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 138 | |
| 139 | Image formats: |
| 140 | -------------- |
| 141 | |
Nishanth Menon | 96a5f18 | 2023-07-27 13:58:52 -0500 | [diff] [blame] | 142 | - tiboot3.bin |
Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 143 | |
Nishanth Menon | 96a5f18 | 2023-07-27 13:58:52 -0500 | [diff] [blame] | 144 | .. image:: img/multi_cert_tiboot3.bin.svg |
Heinrich Schuchardt | bcd233b | 2023-08-22 11:40:57 -0500 | [diff] [blame] | 145 | :alt: tiboot3.bin image format |
Vignesh Raghavendra | 2520546 | 2022-05-25 13:38:50 +0530 | [diff] [blame] | 146 | |
| 147 | - tispl.bin |
| 148 | |
Nishanth Menon | 96a5f18 | 2023-07-27 13:58:52 -0500 | [diff] [blame] | 149 | .. image:: img/dm_tispl.bin.svg |
Heinrich Schuchardt | bcd233b | 2023-08-22 11:40:57 -0500 | [diff] [blame] | 150 | :alt: tispl.bin image format |
Judith Mendez | 964f972 | 2023-03-31 15:36:15 -0500 | [diff] [blame] | 151 | |
Nikhil M Jain | a9b1204 | 2023-07-18 14:27:35 +0530 | [diff] [blame] | 152 | A53 SPL DDR Memory Layout |
| 153 | ------------------------- |
| 154 | |
Nishanth Menon | 3dc51b9 | 2023-07-27 13:58:53 -0500 | [diff] [blame] | 155 | .. am62x_evm_rst_include_start_ddr_mem_layout |
| 156 | |
Nikhil M Jain | a9b1204 | 2023-07-18 14:27:35 +0530 | [diff] [blame] | 157 | This provides an overview memory usage in A53 SPL stage. |
| 158 | |
| 159 | .. list-table:: |
| 160 | :widths: 16 16 16 |
| 161 | :header-rows: 1 |
| 162 | |
| 163 | * - Region |
| 164 | - Start Address |
| 165 | - End Address |
| 166 | |
| 167 | * - EMPTY |
| 168 | - 0x80000000 |
| 169 | - 0x80080000 |
| 170 | |
| 171 | * - TEXT BASE |
| 172 | - 0x80080000 |
| 173 | - 0x800d8000 |
| 174 | |
| 175 | * - EMPTY |
| 176 | - 0x800d8000 |
| 177 | - 0x80200000 |
| 178 | |
| 179 | * - BMP IMAGE |
| 180 | - 0x80200000 |
| 181 | - 0x80b77660 |
| 182 | |
| 183 | * - STACK |
| 184 | - 0x80b77660 |
| 185 | - 0x80b77e60 |
| 186 | |
| 187 | * - GD |
| 188 | - 0x80b77e60 |
| 189 | - 0x80b78000 |
| 190 | |
| 191 | * - MALLOC |
| 192 | - 0x80b78000 |
| 193 | - 0x80b80000 |
| 194 | |
| 195 | * - EMPTY |
| 196 | - 0x80b80000 |
| 197 | - 0x80c80000 |
| 198 | |
| 199 | * - BSS |
| 200 | - 0x80c80000 |
| 201 | - 0x80d00000 |
| 202 | |
| 203 | * - BLOBS |
| 204 | - 0x80d00000 |
| 205 | - 0x80d00400 |
| 206 | |
| 207 | * - EMPTY |
| 208 | - 0x80d00400 |
| 209 | - 0x81000000 |
Nishanth Menon | 3dc51b9 | 2023-07-27 13:58:53 -0500 | [diff] [blame] | 210 | .. am62x_evm_rst_include_end_ddr_mem_layout |
Nikhil M Jain | a9b1204 | 2023-07-18 14:27:35 +0530 | [diff] [blame] | 211 | |
Judith Mendez | 964f972 | 2023-03-31 15:36:15 -0500 | [diff] [blame] | 212 | Switch Setting for Boot Mode |
| 213 | ---------------------------- |
| 214 | |
| 215 | Boot Mode pins provide means to select the boot mode and options before the |
| 216 | device is powered up. After every POR, they are the main source to populate |
| 217 | the Boot Parameter Tables. |
| 218 | |
| 219 | The following table shows some common boot modes used on AM62 platform. More |
| 220 | details can be found in the Technical Reference Manual: |
| 221 | https://www.ti.com/lit/pdf/spruiv7 under the `Boot Mode Pins` section. |
| 222 | |
Nishanth Menon | 5807ae8 | 2023-07-27 13:58:54 -0500 | [diff] [blame] | 223 | .. list-table:: Boot Modes |
| 224 | :widths: 16 16 16 |
| 225 | :header-rows: 1 |
| 226 | |
| 227 | * - Switch Label |
| 228 | - SW2: 12345678 |
| 229 | - SW3: 12345678 |
| 230 | |
| 231 | * - SD |
| 232 | - 01000000 |
| 233 | - 11000010 |
| 234 | |
| 235 | * - OSPI |
| 236 | - 00000000 |
| 237 | - 11001110 |
| 238 | |
| 239 | * - EMMC |
| 240 | - 00000000 |
| 241 | - 11010010 |
| 242 | |
| 243 | * - UART |
| 244 | - 00000000 |
| 245 | - 11011100 |
Judith Mendez | 964f972 | 2023-03-31 15:36:15 -0500 | [diff] [blame] | 246 | |
Nishanth Menon | 5807ae8 | 2023-07-27 13:58:54 -0500 | [diff] [blame] | 247 | * - USB DFU |
| 248 | - 00000000 |
| 249 | - 11001010 |
Judith Mendez | 964f972 | 2023-03-31 15:36:15 -0500 | [diff] [blame] | 250 | |
| 251 | For SW2 and SW1, the switch state in the "ON" position = 1. |
Jason Kacines | b0fdee9 | 2023-08-03 01:29:22 -0500 | [diff] [blame] | 252 | |
| 253 | Debugging U-Boot |
| 254 | ---------------- |
| 255 | |
| 256 | See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for |
| 257 | detailed setup information. |
| 258 | |
| 259 | .. warning:: |
| 260 | |
| 261 | **OpenOCD support since**: v0.12.0 |
| 262 | |
| 263 | If the default package version of OpenOCD in your development |
| 264 | environment's distribution needs to be updated, it might be necessary to |
| 265 | build OpenOCD from the source. |
| 266 | |
| 267 | .. include:: k3.rst |
| 268 | :start-after: .. k3_rst_include_start_openocd_connect_XDS110 |
| 269 | :end-before: .. k3_rst_include_end_openocd_connect_XDS110 |
| 270 | |
| 271 | To start OpenOCD and connect to the board |
| 272 | |
| 273 | .. code-block:: bash |
| 274 | |
| 275 | openocd -f board/ti_am625evm.cfg |