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git01.mediatek.com / filogic / uboot / 4ef529e0f28cf4945edcfb0db9a601ec2fe90daf / . / include / power / rk8xx_pmic.h
blob: 589f8c4e1a93e00be36695dc5b6a136535d87298 [file] [log] [blame]
Simon Glassa8bd2ac2016-01-21 19:43:29 -0700[diff] [blame]1/*
2 * Copyright (C) 2015 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]8#ifndef _PMIC_RK8XX_H_
9#define _PMIC_RK8XX_H_
Simon Glassa8bd2ac2016-01-21 19:43:29 -0700[diff] [blame]10
11enum {
Jacob Chen0237cfd2017-05-02 14:54:48 +0800[diff] [blame]12 REG_SECONDS = 0x00,
13 REG_MINUTES,
14 REG_HOURS,
15 REG_DAYS,
16 REG_MONTHS,
17 REG_YEARS,
18 REG_WEEKS,
19 REG_ALARM_SECONDS,
20 REG_ALARM_MINUTES,
21 REG_ALARM_HOURS,
22 REG_ALARM_DAYS,
23 REG_ALARM_MONTHS,
24 REG_ALARM_YEARS,
25
26 REG_RTC_CTRL = 0x10,
27 REG_RTC_STATUS,
28 REG_RTC_INT,
29 REG_RTC_COMP_LSB,
30 REG_RTC_COMP_MSB,
31
32 ID_MSB = 0x17,
33 ID_LSB,
34
35 REG_CLK32OUT = 0x20,
36 REG_VB_MON,
37 REG_THERMAL,
38 REG_DCDC_EN,
Simon Glassa8bd2ac2016-01-21 19:43:29 -0700[diff] [blame]39 REG_LDO_EN,
40 REG_SLEEP_SET_OFF1,
41 REG_SLEEP_SET_OFF2,
42 REG_DCDC_UV_STS,
Simon Glassa8bd2ac2016-01-21 19:43:29 -0700[diff] [blame]43 REG_DCDC_UV_ACT,
44 REG_LDO_UV_STS,
45 REG_LDO_UV_ACT,
46 REG_DCDC_PG,
47 REG_LDO_PG,
48 REG_VOUT_MON_TDB,
49 REG_BUCK1_CONFIG,
50 REG_BUCK1_ON_VSEL,
Simon Glassa8bd2ac2016-01-21 19:43:29 -0700[diff] [blame]51 REG_BUCK1_SLP_VSEL,
52 REG_BUCK1_DVS_VSEL,
53 REG_BUCK2_CONFIG,
54 REG_BUCK2_ON_VSEL,
55 REG_BUCK2_SLP_VSEL,
56 REG_BUCK2_DVS_VSEL,
57 REG_BUCK3_CONFIG,
58 REG_BUCK4_CONFIG,
Simon Glassa8bd2ac2016-01-21 19:43:29 -0700[diff] [blame]59 REG_BUCK4_ON_VSEL,
60 REG_BUCK4_SLP_VSEL,
Jacob Chen0237cfd2017-05-02 14:54:48 +0800[diff] [blame]61 REG_BOOST_CONFIG_REG,
62 REG_LDO1_ON_VSEL,
63 REG_LDO1_SLP_VSEL,
64 REG_LDO2_ON_VSEL,
65 REG_LDO2_SLP_VSEL,
66 REG_LDO3_ON_VSEL,
67 REG_LDO3_SLP_VSEL,
68 REG_LDO4_ON_VSEL,
69 REG_LDO4_SLP_VSEL,
70 REG_LDO5_ON_VSEL,
71 REG_LDO5_SLP_VSEL,
72 REG_LDO6_ON_VSEL,
73 REG_LDO6_SLP_VSEL,
74 REG_LDO7_ON_VSEL,
75 REG_LDO7_SLP_VSEL,
76 REG_LDO8_ON_VSEL,
77 REG_LDO8_SLP_VSEL,
78 REG_DEVCTRL,
79 REG_INT_STS1,
80 REG_INT_STS_MSK1,
81 REG_INT_STS2,
82 REG_INT_STS_MSK2,
83 REG_IO_POL,
84 REG_OTP_VDD_EN,
85 REG_H5V_EN,
86 REG_SLEEP_SET_OFF,
87 REG_BOOST_LDO9_ON_VSEL,
88 REG_BOOST_LDO9_SLP_VSEL,
89 REG_BOOST_CTRL,
Simon Glassa8bd2ac2016-01-21 19:43:29 -0700[diff] [blame]90
91 /* Not sure what this does */
Jacob Chen0237cfd2017-05-02 14:54:48 +0800[diff] [blame]92 REG_DCDC_ILMAX = 0x90,
93 REG_CHRG_COMP = 0x9a,
94 REG_SUP_STS = 0xa0,
95 REG_USB_CTRL,
96 REG1_CHRG_CTRL,
97 REG2_CHRG_CTRL,
98 REG3_CHRG_CTRL,
99 REG_BAT_CTRL,
100 REG_BAT_HTS_TS1,
101 REG_BAT_LTS_TS1,
102 REG_BAT_HTS_TS2,
103 REG_BAT_LTS_TS2,
104 REG_TS_CTRL,
105 REG_ADC_CTRL,
106 REG_ON_SOURCE,
107 REG_OFF_SOURCE,
108 REG_GGCON,
109 REG_GGSTS,
110 REG_FRAME_SMP_INTERV,
111 REG_AUTO_SLP_CUR_THR,
112 REG3_GASCNT_CAL,
113 REG2_GASCNT_CAL,
114 REG1_GASCNT_CAL,
115 REG0_GASCNT_CAL,
116 REG3_GASCNT,
117 REG2_GASCNT,
118 REG1_GASCNT,
119 REG0_GASCNT,
120 REGH_BAT_CUR_AVG,
121 REGL_BAT_CUR_AVG,
122 REGH_TS1_ADC,
123 REGL_TS1_ADC,
124 REGH_TS2_ADC,
125 REGL_TS2_ADC,
126 REGH_BAT_OCV,
127 REGL_BAT_OCV,
128 REGH_BAT_VOL,
129 REGL_BAT_VOL,
130 REGH_RELAX_ENTRY_THRES,
131 REGL_RELAX_ENTRY_THRES,
132 REGH_RELAX_EXIT_THRES,
133 REGL_RELAX_EXIT_THRES,
134 REGH_RELAX_VOL1,
135 REGL_RELAX_VOL1,
136 REGH_RELAX_VOL2,
137 REGL_RELAX_VOL2,
138 REGH_BAT_CUR_R_CALC,
139 REGL_BAT_CUR_R_CALC,
140 REGH_BAT_VOL_R_CALC,
141 REGL_BAT_VOL_R_CALC,
142 REGH_CAL_OFFSET,
143 REGL_CAL_OFFSET,
144 REG_NON_ACT_TIMER_CNT,
145 REGH_VCALIB0,
146 REGL_VCALIB0,
147 REGH_VCALIB1,
148 REGL_VCALIB1,
149 REGH_IOFFSET,
150 REGL_IOFFSET,
151 REG_SOC,
152 REG3_REMAIN_CAP,
153 REG2_REMAIN_CAP,
154 REG1_REMAIN_CAP,
155 REG0_REMAIN_CAP,
156 REG_UPDAT_LEVE,
157 REG3_NEW_FCC,
158 REG2_NEW_FCC,
159 REG1_NEW_FCC,
160 REG0_NEW_FCC,
161 REG_NON_ACT_TIMER_CNT_SAVE,
162 REG_OCV_VOL_VALID,
163 REG_REBOOT_CNT,
164 REG_POFFSET,
165 REG_MISC_MARK,
166 REG_HALT_CNT,
167 REGH_CALC_REST,
168 REGL_CALC_REST,
169 SAVE_DATA19,
Simon Glassa8bd2ac2016-01-21 19:43:29 -0700[diff] [blame]170 RK808_NUM_OF_REGS,
171};
172
Jacob Chen0234adb2017-05-02 14:54:49 +0800[diff] [blame]173enum {
174 RK805_ID = 0x8050,
175 RK808_ID = 0x0000,
176 RK818_ID = 0x8180,
177};
178
179#define RK8XX_ID_MSK 0xfff0
180
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]181struct rk8xx_reg_table {
Simon Glassa8bd2ac2016-01-21 19:43:29 -0700[diff] [blame]182 char *name;
183 u8 reg_ctl;
184 u8 reg_vol;
185};
186
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]187struct rk8xx_priv {
Jacob Chen0234adb2017-05-02 14:54:49 +0800[diff] [blame]188 int variant;
189};
190
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]191int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt);
Simon Glassa8bd2ac2016-01-21 19:43:29 -0700[diff] [blame]192
193#endif