blob: 59ba0afb2912caceb46e9281be06a22312d72b4f [file] [log] [blame]
Dirk Eibach81b37932011-01-21 09:31:21 +01001/*
2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibach81b37932011-01-21 09:31:21 +01006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1 /* this is a PPC405 CPU */
Dirk Eibach81b37932011-01-21 09:31:21 +010012#define CONFIG_DLVISION_10G 1 /* on a DLVision-10G board */
13
14#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
15
16/*
17 * Include common defines/options for all AMCC eval boards
18 */
19#define CONFIG_HOSTNAME dlvsion-10g
Dirk Eibach81b37932011-01-21 09:31:21 +010020#include "amcc-common.h"
21
Dirk Eibach9a659572012-04-26 03:54:22 +000022#define CONFIG_BOARD_EARLY_INIT_R
Dirk Eibach6b4b92f2012-04-26 03:54:23 +000023#define CONFIG_MISC_INIT_R
Dirk Eibach81b37932011-01-21 09:31:21 +010024#define CONFIG_LAST_STAGE_INIT
25
26#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
27
28/*
29 * Configure PLL
30 */
31#define PLLMR0_DEFAULT PLLMR0_266_133_66
32#define PLLMR1_DEFAULT PLLMR1_266_133_66
33
Dirk Eibach81b37932011-01-21 09:31:21 +010034#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
35
36/*
37 * Default environment variables
38 */
39#define CONFIG_EXTRA_ENV_SETTINGS \
40 CONFIG_AMCC_DEF_ENV \
41 CONFIG_AMCC_DEF_ENV_POWERPC \
42 CONFIG_AMCC_DEF_ENV_NOR_UPD \
43 "kernel_addr=fc000000\0" \
44 "fdt_addr=fc1e0000\0" \
45 "ramdisk_addr=fc200000\0" \
46 ""
47
48#define CONFIG_PHY_ADDR 4 /* PHY address */
49#define CONFIG_HAS_ETH0
50#define CONFIG_HAS_ETH1
51#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
52#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
53
54/*
55 * Commands additional to the ones defined in amcc-common.h
56 */
Dirk Eibach81b37932011-01-21 09:31:21 +010057
58/*
59 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
60 */
61#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
62
63/* SDRAM timings used in datasheet */
64#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
65#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
66#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
67#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
68#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
69
70/*
71 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
72 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
73 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
74 * The Linux BASE_BAUD define should match this configuration.
75 * baseBaud = cpuClock/(uartDivisor*16)
76 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
77 * set Linux BASE_BAUD to 403200.
78 */
79#define CONFIG_CONS_INDEX 1 /* Use UART0 */
80#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
81#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
82#define CONFIG_SYS_BASE_BAUD 691200
83
84/*
85 * I2C stuff
86 */
Dirk Eibachd9adcd72014-07-03 09:28:19 +020087#define CONFIG_SYS_I2C_PPC4XX
88#define CONFIG_SYS_I2C_PPC4XX_CH0
Dirk Eibach42b204f2013-04-25 02:40:01 +000089#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
Dirk Eibachd9adcd72014-07-03 09:28:19 +020090#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
Dirk Eibach81b37932011-01-21 09:31:21 +010091
Dirk Eibachb9577432014-07-03 09:28:18 +020092#define CONFIG_SYS_I2C_IHS
Dirk Eibachfbb4e532015-10-28 11:46:28 +010093#define CONFIG_SYS_I2C_IHS_DUAL
Dirk Eibachb9577432014-07-03 09:28:18 +020094#define CONFIG_SYS_I2C_IHS_CH0
95#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
96#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
Dirk Eibachfbb4e532015-10-28 11:46:28 +010097#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
98#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
Dirk Eibachb9577432014-07-03 09:28:18 +020099#define CONFIG_SYS_I2C_IHS_CH1
100#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
101#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
Dirk Eibachfbb4e532015-10-28 11:46:28 +0100102#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
103#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
Dirk Eibachb9577432014-07-03 09:28:18 +0200104
Dirk Eibachfbb4e532015-10-28 11:46:28 +0100105#define CONFIG_SYS_SPD_BUS_NUM 4
Dirk Eibachb9577432014-07-03 09:28:18 +0200106
Dirk Eibach81b37932011-01-21 09:31:21 +0100107/* Temp sensor/hwmon/dtt */
Dirk Eibach81b37932011-01-21 09:31:21 +0100108
Dirk Eibachfbb4e532015-10-28 11:46:28 +0100109#define CONFIG_SYS_ICS8N3QV01_I2C {1, 3}
110#define CONFIG_SYS_SIL1178_I2C {0, 2}
111#define CONFIG_SYS_DP501_I2C {0, 2}
Dirk Eibachd9adcd72014-07-03 09:28:19 +0200112
Dirk Eibach81b37932011-01-21 09:31:21 +0100113/* EBC peripherals */
114
115#define CONFIG_SYS_FLASH_BASE 0xFC000000
116#define CONFIG_SYS_FPGA0_BASE 0x7f100000
117#define CONFIG_SYS_FPGA1_BASE 0x7f200000
118#define CONFIG_SYS_LATCH_BASE 0x7f300000
119
120#define CONFIG_SYS_FPGA_BASE(k) \
121 (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
122
123#define CONFIG_SYS_FPGA_DONE(k) \
124 (k ? 0x2000 : 0x1000)
125
126#define CONFIG_SYS_FPGA_COUNT 2
127
Dirk Eibach20614a22013-06-26 16:04:26 +0200128#define CONFIG_SYS_FPGA_PTR { \
129 (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
130 (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
131
132#define CONFIG_SYS_FPGA_COMMON
133
Dirk Eibach81b37932011-01-21 09:31:21 +0100134#define CONFIG_SYS_LATCH0_RESET 0xffff
135#define CONFIG_SYS_LATCH0_BOOT 0xffff
Dirk Eibach4761a592013-08-09 10:52:54 +0200136#define CONFIG_SYS_LATCH1_RESET 0xffbf
Dirk Eibach81b37932011-01-21 09:31:21 +0100137#define CONFIG_SYS_LATCH1_BOOT 0xffff
138
Dirk Eibacha46eb6e2011-04-06 13:53:46 +0200139#define CONFIG_SYS_FPGA_NO_RFL_HI
140
Dirk Eibach81b37932011-01-21 09:31:21 +0100141/*
142 * FLASH organization
143 */
144#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
145#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
146
147#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
148
149#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
150#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
151
152#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
153#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
154
155#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
Dirk Eibach81b37932011-01-21 09:31:21 +0100156
157#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
158#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
159
160#ifdef CONFIG_ENV_IS_IN_FLASH
161#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
162#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
163#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
164
165/* Address and size of Redundant Environment Sector */
166#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
167#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
168#endif
169
170/*
171 * PPC405 GPIO Configuration
172 */
173#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
174{ \
175/* GPIO Core 0 */ \
176{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
177{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
178{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
179{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
180{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
181{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
182{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
183{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
184{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
185{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
186{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
187{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
188{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
189{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
190{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
191{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
192{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
193{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
194{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
195{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
196{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
197{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
198{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
199{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
200{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
201{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
202{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
203{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
204{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
205{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
206{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
207{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
208} \
209}
210
211/*
212 * Definitions for initial stack pointer and data area (in data cache)
213 */
214/* use on chip memory (OCM) for temperary stack until sdram is tested */
215#define CONFIG_SYS_TEMP_STACK_OCM 1
216
217/* On Chip Memory location */
218#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
219#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
220#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
York Sun515fbb42016-04-06 13:22:10 -0700221#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
Dirk Eibach81b37932011-01-21 09:31:21 +0100222
Dirk Eibach81b37932011-01-21 09:31:21 +0100223#define CONFIG_SYS_GBL_DATA_OFFSET \
York Sun515fbb42016-04-06 13:22:10 -0700224 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dirk Eibach81b37932011-01-21 09:31:21 +0100225#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
226
227/*
228 * External Bus Controller (EBC) Setup
229 */
230
231/* Memory Bank 0 (NOR-flash) */
232#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_ENABLED | \
233 EBC_BXAP_FWT_ENCODE(8) | \
234 EBC_BXAP_BWT_ENCODE(7) | \
235 EBC_BXAP_BCE_DISABLE | \
236 EBC_BXAP_BCT_2TRANS | \
237 EBC_BXAP_CSN_ENCODE(0) | \
238 EBC_BXAP_OEN_ENCODE(2) | \
239 EBC_BXAP_WBN_ENCODE(2) | \
240 EBC_BXAP_WBF_ENCODE(2) | \
241 EBC_BXAP_TH_ENCODE(4) | \
242 EBC_BXAP_RE_DISABLED | \
243 EBC_BXAP_SOR_NONDELAYED | \
244 EBC_BXAP_BEM_WRITEONLY | \
245 EBC_BXAP_PEN_DISABLED)
246#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
247 EBC_BXCR_BS_64MB | \
248 EBC_BXCR_BU_RW | \
249 EBC_BXCR_BW_16BIT)
250
251/* Memory Bank 1 (FPGA0) */
252#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
253 EBC_BXAP_TWT_ENCODE(5) | \
254 EBC_BXAP_BCE_DISABLE | \
255 EBC_BXAP_BCT_2TRANS | \
256 EBC_BXAP_CSN_ENCODE(0) | \
257 EBC_BXAP_OEN_ENCODE(2) | \
258 EBC_BXAP_WBN_ENCODE(1) | \
259 EBC_BXAP_WBF_ENCODE(1) | \
260 EBC_BXAP_TH_ENCODE(0) | \
261 EBC_BXAP_RE_DISABLED | \
262 EBC_BXAP_SOR_NONDELAYED | \
263 EBC_BXAP_BEM_WRITEONLY | \
264 EBC_BXAP_PEN_DISABLED)
265#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
266 EBC_BXCR_BS_1MB | \
267 EBC_BXCR_BU_RW | \
268 EBC_BXCR_BW_16BIT)
269
270/* Memory Bank 2 (FPGA1) */
271#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
272 EBC_BXAP_TWT_ENCODE(6) | \
273 EBC_BXAP_BCE_DISABLE | \
274 EBC_BXAP_BCT_2TRANS | \
275 EBC_BXAP_CSN_ENCODE(0) | \
276 EBC_BXAP_OEN_ENCODE(2) | \
277 EBC_BXAP_WBN_ENCODE(1) | \
278 EBC_BXAP_WBF_ENCODE(1) | \
279 EBC_BXAP_TH_ENCODE(0) | \
280 EBC_BXAP_RE_DISABLED | \
281 EBC_BXAP_SOR_NONDELAYED | \
282 EBC_BXAP_BEM_WRITEONLY | \
283 EBC_BXAP_PEN_DISABLED)
284#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
285 EBC_BXCR_BS_1MB | \
286 EBC_BXCR_BU_RW | \
287 EBC_BXCR_BW_16BIT)
288
289/* Memory Bank 3 (Latches) */
290#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
291 EBC_BXAP_FWT_ENCODE(8) | \
292 EBC_BXAP_BWT_ENCODE(4) | \
293 EBC_BXAP_BCE_DISABLE | \
294 EBC_BXAP_BCT_2TRANS | \
295 EBC_BXAP_CSN_ENCODE(0) | \
296 EBC_BXAP_OEN_ENCODE(1) | \
297 EBC_BXAP_WBN_ENCODE(1) | \
298 EBC_BXAP_WBF_ENCODE(1) | \
299 EBC_BXAP_TH_ENCODE(2) | \
300 EBC_BXAP_RE_DISABLED | \
301 EBC_BXAP_SOR_NONDELAYED | \
302 EBC_BXAP_BEM_WRITEONLY | \
303 EBC_BXAP_PEN_DISABLED)
304#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
305 EBC_BXCR_BS_1MB | \
306 EBC_BXCR_BU_RW | \
307 EBC_BXCR_BW_16BIT)
308
309/*
310 * OSD Setup
311 */
Dirk Eibachc0413ee2011-04-06 13:53:48 +0200312#define CONFIG_SYS_MPC92469AC
Dirk Eibach81b37932011-01-21 09:31:21 +0100313#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
Dirk Eibachfbb4e532015-10-28 11:46:28 +0100314#define CONFIG_SYS_DP501_DIFFERENTIAL
315#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
Dirk Eibach81b37932011-01-21 09:31:21 +0100316
317#endif /* __CONFIG_H */