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Masahiro Yamadacc85b7b2015-07-26 02:46:26 +09001#
2# Multifunction miscellaneous devices
3#
4
5menu "Multifunction device drivers"
6
Thomas Choub1ed6862015-10-07 20:20:51 +08007config MISC
8 bool "Enable Driver Model for Misc drivers"
9 depends on DM
10 help
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
14 access the device.
15
Thomas Chou36b9c9a2015-10-14 08:43:31 +080016config ALTERA_SYSID
17 bool "Altera Sysid support"
18 depends on MISC
19 help
20 Select this to enable a sysid for Altera devices. Please find
21 details on the "Embedded Peripherals IP User Guide" of Altera.
22
Simon Glass5b79bb22015-02-13 12:20:47 -070023config CMD_CROS_EC
24 bool "Enable crosec command"
25 depends on CROS_EC
26 help
27 Enable command-line access to the Chrome OS EC (Embedded
28 Controller). This provides the 'crosec' command which has
29 a number of sub-commands for performing EC tasks such as
30 updating its flash, accessing a small saved context area
31 and talking to the I2C bus behind the EC (if there is one).
32
33config CROS_EC
34 bool "Enable Chrome OS EC"
35 help
36 Enable access to the Chrome OS EC. This is a separate
37 microcontroller typically available on a SPI bus on Chromebooks. It
38 provides access to the keyboard, some internal storage and may
39 control access to the battery and main PMIC depending on the
40 device. You can use the 'crosec' command to access it.
41
42config CROS_EC_I2C
43 bool "Enable Chrome OS EC I2C driver"
44 depends on CROS_EC
45 help
46 Enable I2C access to the Chrome OS EC. This is used on older
47 ARM Chromebooks such as snow and spring before the standard bus
48 changed to SPI. The EC will accept commands across the I2C using
49 a special message protocol, and provide responses.
50
51config CROS_EC_LPC
52 bool "Enable Chrome OS EC LPC driver"
53 depends on CROS_EC
54 help
55 Enable I2C access to the Chrome OS EC. This is used on x86
56 Chromebooks such as link and falco. The keyboard is provided
57 through a legacy port interface, so on x86 machines the main
58 function of the EC is power and thermal management.
59
Simon Glassc6e06692015-03-26 09:29:40 -060060config CROS_EC_SANDBOX
61 bool "Enable Chrome OS EC sandbox driver"
62 depends on CROS_EC && SANDBOX
63 help
64 Enable a sandbox emulation of the Chrome OS EC. This supports
65 keyboard (use the -l flag to enable the LCD), verified boot context,
66 EC flash read/write/erase support and a few other things. It is
67 enough to perform a Chrome OS verified boot on sandbox.
68
Simon Glass5b79bb22015-02-13 12:20:47 -070069config CROS_EC_SPI
70 bool "Enable Chrome OS EC SPI driver"
71 depends on CROS_EC
72 help
73 Enable SPI access to the Chrome OS EC. This is used on newer
74 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
75 provides a faster and more robust interface than I2C but the bugs
76 are less interesting.
77
Simon Glass58ed3222017-05-17 03:25:02 -060078config DS4510
79 bool "Enable support for DS4510 CPU supervisor"
80 help
81 Enable support for the Maxim DS4510 CPU supervisor. It has an
82 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
83 and a configurable timer for the supervisor function. The device is
84 connected over I2C.
85
Peng Fanfb6166a2015-08-26 15:41:33 +080086config FSL_SEC_MON
gaurav rana9aaea442015-02-27 09:44:22 +053087 bool "Enable FSL SEC_MON Driver"
88 help
89 Freescale Security Monitor block is responsible for monitoring
90 system states.
91 Security Monitor can be transitioned on any security failures,
92 like software violations or hardware security violations.
Stefan Roese04b22752015-03-12 11:22:46 +010093
Peng Fane1872252015-08-27 14:49:05 +080094config MXC_OCOTP
95 bool "Enable MXC OCOTP Driver"
96 help
97 If you say Y here, you will get support for the One Time
98 Programmable memory pages that are stored on the some
99 Freescale i.MX processors.
100
Stefan Roese4a269f22016-07-19 07:45:46 +0200101config NUVOTON_NCT6102D
102 bool "Enable Nuvoton NCT6102D Super I/O driver"
103 help
104 If you say Y here, you will get support for the Nuvoton
105 NCT6102D Super I/O driver. This can be used to enable or
106 disable the legacy UART, the watchdog or other devices
107 in the Nuvoton Super IO chips on X86 platforms.
108
Simon Glassc9795172016-01-21 19:43:31 -0700109config PWRSEQ
110 bool "Enable power-sequencing drivers"
111 depends on DM
112 help
113 Power-sequencing drivers provide support for controlling power for
114 devices. They are typically referenced by a phandle from another
115 device. When the device is started up, its power sequence can be
116 initiated.
117
118config SPL_PWRSEQ
119 bool "Enable power-sequencing drivers for SPL"
120 depends on PWRSEQ
121 help
122 Power-sequencing drivers provide support for controlling power for
123 devices. They are typically referenced by a phandle from another
124 device. When the device is started up, its power sequence can be
125 initiated.
126
Stefan Roese04b22752015-03-12 11:22:46 +0100127config PCA9551_LED
128 bool "Enable PCA9551 LED driver"
129 help
130 Enable driver for PCA9551 LED controller. This controller
131 is connected via I2C. So I2C needs to be enabled.
132
133config PCA9551_I2C_ADDR
134 hex "I2C address of PCA9551 LED controller"
135 depends on PCA9551_LED
136 default 0x60
137 help
138 The I2C address of the PCA9551 LED controller.
Simon Glass14000862015-06-23 15:39:13 -0600139
Stephen Warrenf6417002016-09-13 10:45:57 -0600140config TEGRA_CAR
141 bool "Enable support for the Tegra CAR driver"
142 depends on TEGRA_NO_BPMP
143 help
144 The Tegra CAR (Clock and Reset Controller) is a HW module that
145 controls almost all clocks and resets in a Tegra SoC.
146
Stephen Warrena2148922016-08-08 09:41:34 -0600147config TEGRA186_BPMP
148 bool "Enable support for the Tegra186 BPMP driver"
149 depends on TEGRA186
150 help
151 The Tegra BPMP (Boot and Power Management Processor) is a separate
152 auxiliary CPU embedded into Tegra to perform power management work,
153 and controls related features such as clocks, resets, power domains,
154 PMIC I2C bus, etc. This driver provides the core low-level
155 communication path by which feature-specific drivers (such as clock)
156 can make requests to the BPMP. This driver is similar to an MFD
157 driver in the Linux kernel.
158
Stefan Roeseba019ed2016-01-19 14:05:10 +0100159config WINBOND_W83627
160 bool "Enable Winbond Super I/O driver"
161 help
162 If you say Y here, you will get support for the Winbond
163 W83627 Super I/O driver. This can be used to enable the
164 legacy UART or other devices in the Winbond Super IO chips
165 on X86 platforms.
166
Miao Yan4fcd7f22016-05-22 19:37:14 -0700167config QFW
168 bool
169 help
170 Hidden option to enable QEMU fw_cfg interface. This will be selected by
Miao Yan92106272016-05-22 19:37:17 -0700171 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
Miao Yan4fcd7f22016-05-22 19:37:14 -0700172
mario.six@gdsys.cc7559ac42016-06-22 15:14:16 +0200173config I2C_EEPROM
174 bool "Enable driver for generic I2C-attached EEPROMs"
175 depends on MISC
176 help
177 Enable a generic driver for EEPROMs attached via I2C.
Masahiro Yamadacc85b7b2015-07-26 02:46:26 +0900178endmenu