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git01.mediatek.com / filogic / uboot / 4e7cdcf48dfa1de12b7929617964999e2e399965 / . / configs / socfpga_is1_defconfig
blob: 68a37f51cdbaa0c7b5baf07cb0003bb74f96ed4d [file] [log] [blame]
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_SOCFPGA=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]3CONFIG_SYS_TEXT_BASE=0x01000040
Masahiro Yamada75794f92016-09-19 21:40:26 +0900[diff] [blame]4CONFIG_SYS_MALLOC_F_LEN=0x2000
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]5CONFIG_TARGET_SOCFPGA_IS1=y
Tom Rini9bd09622018-04-07 20:27:54 -0400[diff] [blame]6CONFIG_SPL=y
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]7CONFIG_SPL_STACK_R_ADDR=0x00800000
8CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
Tom Rini732aa4a2018-02-10 16:54:38 -0500[diff] [blame]9CONFIG_DISTRO_DEFAULTS=y
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]10CONFIG_FIT=y
Sam Protsenkobd7bffe2017-08-14 20:22:17 +0300[diff] [blame]11CONFIG_USE_BOOTARGS=y
12CONFIG_BOOTARGS="console=ttyS0,115200"
Tom Rini732aa4a2018-02-10 16:54:38 -0500[diff] [blame]13# CONFIG_USE_BOOTCOMMAND is not set
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]14CONFIG_SYS_CONSOLE_IS_IN_ENV=y
Simon Glassac3ee422016-10-17 20:12:59 -0600[diff] [blame]15CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
Simon Glass217652f2016-10-17 20:12:58 -0600[diff] [blame]16CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
Heiko Schocher20ea7ab2016-09-09 08:12:49 +0200[diff] [blame]17CONFIG_VERSION_VARIABLE=y
Lokesh Vutla94d95e42016-10-11 21:33:46 -0400[diff] [blame]18# CONFIG_DISPLAY_BOARDINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]19CONFIG_DISPLAY_BOARDINFO_LATE=y
Simon Glassffe19762016-09-12 23:18:22 -0600[diff] [blame]20CONFIG_SPL_STACK_R=y
Marek Vasute2542252018-04-07 16:05:27 +0200[diff] [blame]21CONFIG_SPL_SPI_LOAD=y
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]22CONFIG_CMD_ASKENV=y
23CONFIG_CMD_GREPENV=y
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]24# CONFIG_CMD_FLASH is not set
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]25CONFIG_CMD_GPIO=y
26CONFIG_CMD_I2C=y
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]27CONFIG_CMD_SF=y
28CONFIG_CMD_SPI=y
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]29CONFIG_CMD_CACHE=y
30CONFIG_CMD_TIME=y
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]31CONFIG_CMD_EXT4_WRITE=y
Tom Rini5ad8e112017-10-22 17:55:07 -0400[diff] [blame]32CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
33CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
Heiko Schocher09dbb852016-09-21 07:58:19 +0200[diff] [blame]34CONFIG_CMD_UBI=y
Tom Rini2cbc1202018-04-28 10:45:55 -0400[diff] [blame]35# CONFIG_ISO_PARTITION is not set
36# CONFIG_EFI_PARTITION is not set
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]37CONFIG_ENV_IS_IN_SPI_FLASH=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]38CONFIG_SPL_DM=y
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]39CONFIG_SPL_DM_SEQ_ALIAS=y
Lukasz Majewski6dd8c902018-02-09 23:50:57 +0100[diff] [blame]40CONFIG_BOOTCOUNT_LIMIT=y
Tom Rinic98ed5f2018-02-24 16:50:41 -0500[diff] [blame]41CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
Tien Fong Cheecde42192017-07-26 13:05:40 +0800[diff] [blame]42CONFIG_FPGA_SOCFPGA=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]43CONFIG_DM_GPIO=y
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]44CONFIG_DWAPB_GPIO=y
Dinh Nguyena75fcc12018-04-04 17:18:21 -0500[diff] [blame]45CONFIG_DM_I2C=y
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]46CONFIG_SYS_I2C_DW=y
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]47# CONFIG_MMC is not set
Adam Fordac44a302018-07-07 22:18:22 -0500[diff] [blame]48CONFIG_MTD_DEVICE=y
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]49CONFIG_SPI_FLASH=y
50CONFIG_SPI_FLASH_BAR=y
51CONFIG_SPI_FLASH_STMICRO=y
Alexandru Gagniuc4e24ff62017-08-01 17:20:00 -0700[diff] [blame]52CONFIG_PHY_MICREL=y
53CONFIG_PHY_MICREL_KSZ90X1=y
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]54CONFIG_DM_ETH=y
55CONFIG_ETH_DESIGNWARE=y
Dinh Nguyenbfddbb22018-04-04 17:18:25 -0500[diff] [blame]56CONFIG_DM_RESET=y
Adam Ford4e96ff82018-04-15 13:51:26 -0400[diff] [blame]57CONFIG_SPI=y
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]58CONFIG_CADENCE_QSPI=y