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Alessandro Rubinibb930d12009-01-24 18:10:37 +01001/*
2 * (C) Copyright 2005
3 * STMicrolelctronics, <www.st.com>
4 *
5 * (C) Copyright 2004
6 * ARM Ltd.
7 * Philippe Robin, <philippe.robin@arm.com>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <asm/io.h>
Alessandro Rubini94ecf972009-07-24 11:27:14 +020030#include <asm/arch/gpio.h>
Alessandro Rubinibb930d12009-01-24 18:10:37 +010031
32DECLARE_GLOBAL_DATA_PTR;
33
34#ifdef CONFIG_SHOW_BOOT_PROGRESS
35void show_boot_progress(int progress)
36{
37 printf("%i\n", progress);
38}
39#endif
40
41/*
42 * Miscellaneous platform dependent initialisations
43 */
44int board_init(void)
45{
46 gd->bd->bi_arch_number = MACH_TYPE_NOMADIK;
47 gd->bd->bi_boot_params = 0x00000100;
48 writel(0xC37800F0, NOMADIK_GPIO1_BASE + 0x20);
49 writel(0x00000000, NOMADIK_GPIO1_BASE + 0x24);
50 writel(0x00000000, NOMADIK_GPIO1_BASE + 0x28);
51 writel(readl(NOMADIK_SRC_BASE) | 0x8000, NOMADIK_SRC_BASE);
52
Alessandro Rubinic2be3a92009-02-09 15:53:33 +010053 /* Set up SMCS1 for Ethernet: sram-like, enabled, timing values */
54 writel(0x0000305b, REG_FSMC_BCR1);
55 writel(0x00033f33, REG_FSMC_BTR1);
Alessandro Rubinibb930d12009-01-24 18:10:37 +010056
Alessandro Rubini0d8dafa2009-06-22 09:18:57 +020057 /* Set up SMCS0 for OneNand: sram-like once again */
58 writel(0x000030db, NOMADIK_FSMC_BASE + 0x00); /* FSMC_BCR0 */
59 writel(0x02100551, NOMADIK_FSMC_BASE + 0x04); /* FSMC_BTR0 */
60
Alessandro Rubinic2be3a92009-02-09 15:53:33 +010061 icache_enable();
Alessandro Rubinibb930d12009-01-24 18:10:37 +010062 return 0;
63}
64
Alessandro Rubini94ecf972009-07-24 11:27:14 +020065int board_late_init(void)
Alessandro Rubinibb930d12009-01-24 18:10:37 +010066{
Alessandro Rubini94ecf972009-07-24 11:27:14 +020067 /* Set the two I2C gpio lines to be gpio high */
68 nmk_gpio_set(__SCL, 1); nmk_gpio_set(__SDA, 1);
69 nmk_gpio_dir(__SCL, 1); nmk_gpio_dir(__SDA, 1);
70 nmk_gpio_af(__SCL, GPIO_GPIO); nmk_gpio_af(__SDA, GPIO_GPIO);
71
72 /* Reset the I2C port expander, on GPIO77 */
73 nmk_gpio_af(77, GPIO_GPIO);
74 nmk_gpio_dir(77, 1);
75 nmk_gpio_set(77, 0);
76 udelay(10);
77 nmk_gpio_set(77, 1);
78
Alessandro Rubinibb930d12009-01-24 18:10:37 +010079 return 0;
80}
81
82int dram_init(void)
83{
84 /* set dram bank start addr and size */
85 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
86 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
87
88 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
89 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
90 return 0;
91}