blob: d974af8da1a71cc2460d6bb9fbe86387eb8e8781 [file] [log] [blame]
Heiko Thiery05a3d952022-01-31 17:30:45 +01001// SPDX-License-Identifier: GPL-2.0+
2
3#include "pitx_misc.h"
4#include <common.h>
Sughosh Ganuccb36462022-04-15 11:29:34 +05305#include <efi.h>
6#include <efi_loader.h>
Heiko Thiery05a3d952022-01-31 17:30:45 +01007#include <init.h>
8#include <mmc.h>
9#include <miiphy.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/imx8mq_pins.h>
12#include <asm/arch/sys_proto.h>
13#include <asm-generic/gpio.h>
14#include <asm/mach-imx/gpio.h>
15#include <asm/mach-imx/iomux-v3.h>
16#include <linux/delay.h>
Sughosh Ganuccb36462022-04-15 11:29:34 +053017#include <linux/kernel.h>
Heiko Thiery05a3d952022-01-31 17:30:45 +010018
19DECLARE_GLOBAL_DATA_PTR;
20
21#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
22#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
23
24static iomux_v3_cfg_t const wdog_pads[] = {
25 IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
26};
27
28static iomux_v3_cfg_t const uart_pads[] = {
29 IMX8MQ_PAD_UART3_RXD__UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
30 IMX8MQ_PAD_UART3_TXD__UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
31 IMX8MQ_PAD_ECSPI1_SS0__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
32 IMX8MQ_PAD_ECSPI1_MISO__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
33};
34
Sughosh Ganuccb36462022-04-15 11:29:34 +053035#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT)
36struct efi_fw_image fw_images[] = {
37 {
38 .image_type_id = KONTRON_PITX_IMX8M_FIT_IMAGE_GUID,
39 .fw_name = u"KONTRON-PITX-IMX8M-UBOOT",
40 .image_index = 1,
41 },
42};
43
44struct efi_capsule_update_info update_info = {
45 .dfu_string = "mmc 0=flash-bin raw 0x42 0x1000 mmcpart 1",
46 .images = fw_images,
47};
48
49u8 num_image_type_guids = ARRAY_SIZE(fw_images);
50#endif /* EFI_HAVE_CAPSULE_SUPPORT */
51
Heiko Thiery05a3d952022-01-31 17:30:45 +010052int board_early_init_f(void)
53{
54 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
55
56 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
57 set_wdog_reset(wdog);
58
59 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
60
61 return 0;
62}
63
64int board_phys_sdram_size(phys_size_t *memsize)
65{
66 int variant = 0;
67
68 variant = get_pitx_board_variant();
69
70 switch(variant) {
71 case 2:
72 *memsize = 0x80000000;
73 break;
74 case 3:
75 *memsize = 0x100000000;
76 break;
77 default:
78 printf("Unknown DDR type!!!\n");
79 *memsize = 0x40000000;
80 break;
81 }
82
83 debug("Memsize: %d MiB\n", (int)(*memsize >> 20));
84
85 return 0;
86}
87
88
89#ifdef CONFIG_FEC_MXC
90#define FEC_RST_PAD IMX_GPIO_NR(1, 11)
91static iomux_v3_cfg_t const fec1_rst_pads[] = {
92 IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
93};
94
95static void setup_iomux_fec(void)
96{
97 imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
98 ARRAY_SIZE(fec1_rst_pads));
99}
100
101static int setup_fec(void)
102{
103 struct iomuxc_gpr_base_regs *gpr =
104 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
105
106 setup_iomux_fec();
107
108 /* Use 125M anatop REF_CLK1 for ENET1, not from external */
109 clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
110 return set_clk_enet(ENET_125MHZ);
111}
112
113int board_phy_config(struct phy_device *phydev)
114{
115 unsigned int val;
116
117 /*
118 * Set LED configuration register 1:
119 * LED2_SEL: 0b1011 (link established, blink on activity)
120 */
121 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x18);
122 val &= 0xf0ff;
123 phy_write(phydev, MDIO_DEVAD_NONE, 0x18, val | (0xb << 8));
124
125 if (phydev->drv->config)
126 phydev->drv->config(phydev);
127 return 0;
128}
129#endif
130
131int board_init(void)
132{
133#ifdef CONFIG_FEC_MXC
134 setup_fec();
135#endif
136
137#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3)
138 init_usb_clk();
139#endif
140
141 return 0;
142}
143
144#ifdef CONFIG_MISC_INIT_R
145#define TPM_RESET IMX_GPIO_NR(3, 2)
146#define USBHUB_RESET IMX_GPIO_NR(3, 4)
147
148static void reset_device_by_gpio(const char *label, int pin, int delay_ms)
149{
150 gpio_request(pin, label);
151 gpio_direction_output(pin, 0);
152 mdelay(delay_ms);
153 gpio_direction_output(pin, 1);
154}
155
156int misc_init_r(void)
157{
158 /*
159 * reset TPM chip (Infineon SLB9670) as required by datasheet
160 * (60ms minimum Reset Inactive Time, 70ms implemented)
161 */
162 reset_device_by_gpio("tpm_reset", TPM_RESET, 70);
163
164 /*
165 * reset USB hub as required by datasheet
166 * (3ms minimum reset duration, 10ms implemented)
167 */
168 reset_device_by_gpio("usbhub_reset", USBHUB_RESET, 10);
169
170 return 0;
171}
172#endif
173
174int board_mmc_get_env_dev(int devno)
175{
176 return devno;
177}
178
179uint mmc_get_env_part(struct mmc *mmc)
180{
181 /* part 1 for eMMC, part 1 for SD card */
182 return (mmc_get_env_dev() == 0) ? 1 : 0;
183}
184
185int board_late_init(void)
186{
187 return 0;
188}