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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Ashish Kumar227b4bc2017-08-31 16:12:54 +05302/*
Pramod Kumara0531822018-10-12 14:04:27 +00003 * Copyright 2017-2018 NXP
Ashish Kumar227b4bc2017-08-31 16:12:54 +05304 */
5
6#ifndef __LS1088_COMMON_H
7#define __LS1088_COMMON_H
8
Sumit Garg08da8b22018-01-06 09:04:24 +05309/* SPL build */
10#ifdef CONFIG_SPL_BUILD
11#define SPL_NO_BOARDINFO
12#define SPL_NO_QIXIS
13#define SPL_NO_PCI
14#define SPL_NO_ENV
15#define SPL_NO_RTC
16#define SPL_NO_USB
17#define SPL_NO_SATA
18#define SPL_NO_QSPI
19#define SPL_NO_IFC
Sumit Garg08da8b22018-01-06 09:04:24 +053020#endif
Ashish Kumar227b4bc2017-08-31 16:12:54 +053021
Ashish Kumar227b4bc2017-08-31 16:12:54 +053022#include <asm/arch/stream_id_lsch3.h>
23#include <asm/arch/config.h>
24#include <asm/arch/soc.h>
25
Pramod Kumara0531822018-10-12 14:04:27 +000026#define LS1088ARDB_PB_BOARD 0x4A
Ashish Kumar227b4bc2017-08-31 16:12:54 +053027/* Link Definitions */
Ashish Kumar227b4bc2017-08-31 16:12:54 +053028
29/* Link Definitions */
Ashish Kumar2703ea72017-12-14 17:37:09 +053030#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
Ashish Kumar227b4bc2017-08-31 16:12:54 +053031
Ashish Kumar227b4bc2017-08-31 16:12:54 +053032#define CONFIG_VERY_BIG_RAM
33#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
34#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
35#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
36#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
37#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
38/*
39 * SMP Definitinos
40 */
Michael Wallef056e0f2020-06-01 21:53:26 +020041#define CPU_RELEASE_ADDR secondary_boot_addr
Ashish Kumar227b4bc2017-08-31 16:12:54 +053042
Biwen Lia5c9e122021-02-05 19:01:58 +080043/* GPIO */
Biwen Lia5c9e122021-02-05 19:01:58 +080044
Ashish Kumar227b4bc2017-08-31 16:12:54 +053045/* I2C */
Chuanhua Han8a898462019-07-23 18:43:11 +080046
Ashish Kumar227b4bc2017-08-31 16:12:54 +053047
48/* Serial Port */
Ashish Kumar227b4bc2017-08-31 16:12:54 +053049#define CONFIG_SYS_NS16550_SERIAL
50#define CONFIG_SYS_NS16550_REG_SIZE 1
51#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
52
Ashish Kumar227b4bc2017-08-31 16:12:54 +053053/*
54 * During booting, IFC is mapped at the region of 0x30000000.
55 * But this region is limited to 256MB. To accommodate NOR, promjet
56 * and FPGA. This region is divided as below:
57 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
58 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
59 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
60 *
61 * To accommodate bigger NOR flash and other devices, we will map IFC
62 * chip selects to as below:
63 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
64 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
65 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
66 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
67 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
68 *
69 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
70 * CONFIG_SYS_FLASH_BASE has the final address (core view)
71 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
72 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
73 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
74 */
75
76#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
77#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
78#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
79
80#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
81#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
82
83#ifndef __ASSEMBLY__
84unsigned long long get_qixis_addr(void);
85#endif
86
87#define QIXIS_BASE get_qixis_addr()
88#define QIXIS_BASE_PHYS 0x20000000
89#define QIXIS_BASE_PHYS_EARLY 0xC000000
90
91
92#define CONFIG_SYS_NAND_BASE 0x530000000ULL
93#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
94
95
96/* MC firmware */
97/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
98#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
99#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
100#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
101#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
102#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
103#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
Bogdan Purcareata33ba9392017-10-05 06:56:53 +0000104
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530105/*
106 * Carve out a DDR region which will not be used by u-boot/Linux
107 *
108 * It will be used by MC and Debug Server. The MC region must be
109 * 512MB aligned, so the min size to hide is 512MB.
110 */
111
112#if defined(CONFIG_FSL_MC_ENET)
Meenakshi Aggarwal67f195c2019-02-27 14:41:02 +0530113#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530114#endif
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530115
116/* Miscellaneous configurable options */
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530117
Ashish Kumara179e562017-11-02 09:50:47 +0530118/* SATA */
119#ifdef CONFIG_SCSI
Ashish Kumara179e562017-11-02 09:50:47 +0530120#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
Ashish Kumara179e562017-11-02 09:50:47 +0530121#endif
122
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530123/* Physical Memory Map */
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530124
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530125#define CONFIG_HWCONFIG
126#define HWCONFIG_BUFFER_SIZE 128
127
Sumit Garg08da8b22018-01-06 09:04:24 +0530128#ifndef SPL_NO_ENV
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530129/* Initial environment variables */
130#define CONFIG_EXTRA_ENV_SETTINGS \
131 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
132 "loadaddr=0x80100000\0" \
133 "kernel_addr=0x100000\0" \
134 "ramdisk_addr=0x800000\0" \
135 "ramdisk_size=0x2000000\0" \
136 "fdt_high=0xa0000000\0" \
137 "initrd_high=0xffffffffffffffff\0" \
138 "kernel_start=0x581000000\0" \
139 "kernel_load=0xa0000000\0" \
140 "kernel_size=0x2800000\0" \
141 "console=ttyAMA0,38400n8\0" \
142 "mcinitcmd=fsl_mc start mc 0x580a00000" \
143 " 0x580e00000 \0"
Sumit Garg08da8b22018-01-06 09:04:24 +0530144#endif
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530145
Ashish Kumar5676ceb2017-11-06 13:18:43 +0530146#ifdef CONFIG_SPL
Udit Agarwal22ec2382019-11-07 16:11:32 +0000147#ifdef CONFIG_NXP_ESBC
Sumit Garg19ef0352018-01-06 09:04:25 +0530148#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
149/*
150 * HDR would be appended at end of image and copied to DDR along
151 * with U-Boot image. Here u-boot max. size is 512K. So if binary
152 * size increases then increase this size in case of secure boot as
153 * it uses raw u-boot image instead of fit image.
154 */
155#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
156#else
157#define CONFIG_SYS_MONITOR_LEN 0x100000
Udit Agarwal22ec2382019-11-07 16:11:32 +0000158#endif /* ifdef CONFIG_NXP_ESBC */
Sumit Garg19ef0352018-01-06 09:04:25 +0530159
Ashish Kumar5676ceb2017-11-06 13:18:43 +0530160#endif
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530161#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
162
163#endif /* __LS1088_COMMON_H */