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git01.mediatek.com / filogic / uboot / 4e506b0d1f82e175810c4da4b519f716f67d492b / . / configs / mvebu_db_armada8k_defconfig
blob: 0b4afbe59e847f8d227576132aa74447a7884bc3 [file] [log] [blame]
Stefan Roesed8d20182016-10-25 11:47:51 +0200[diff] [blame]1CONFIG_ARM=y
Adam Fordd36b1022019-08-14 08:29:25 -0500[diff] [blame]2CONFIG_ARCH_CPU_INIT=y
Stefan Roesed8d20182016-10-25 11:47:51 +0200[diff] [blame]3CONFIG_ARCH_MVEBU=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]4CONFIG_SYS_TEXT_BASE=0x00000000
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]5CONFIG_NR_DRAM_BANKS=2
Stefan Roesed8d20182016-10-25 11:47:51 +0200[diff] [blame]6CONFIG_TARGET_MVEBU_ARMADA_8K=y
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]7CONFIG_ENV_SIZE=0x10000
Konstantin Porotchkin855f5d32021-01-18 18:35:54 +0200[diff] [blame]8CONFIG_ENV_OFFSET=0x3f0000
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]9CONFIG_ENV_SECT_SIZE=0x10000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]10CONFIG_DEFAULT_DEVICE_TREE="armada-8040-db"
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]11CONFIG_DEBUG_UART_BASE=0xf0512000
12CONFIG_DEBUG_UART_CLOCK=200000000
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]13CONFIG_SYS_LOAD_ADDR=0x800000
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]14CONFIG_DEBUG_UART=y
Stefan Roesed8d20182016-10-25 11:47:51 +0200[diff] [blame]15CONFIG_AHCI=y
Tom Rinib9baf7f2017-12-18 20:19:09 -0500[diff] [blame]16CONFIG_DISTRO_DEFAULTS=y
Tom Rini4ddbade2022-05-25 12:16:03 -0400[diff] [blame]17CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
18CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
Stefan Roesed8d20182016-10-25 11:47:51 +0200[diff] [blame]19# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
Simon Glass4be229d2019-07-20 20:51:14 -0600[diff] [blame]20CONFIG_USE_PREBOOT=y
Stefan Roesed8d20182016-10-25 11:47:51 +0200[diff] [blame]21CONFIG_SYS_CONSOLE_INFO_QUIET=y
22# CONFIG_DISPLAY_CPUINFO is not set
23# CONFIG_DISPLAY_BOARDINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]24CONFIG_DISPLAY_BOARDINFO_LATE=y
Simon Glass62adede2017-01-23 13:31:19 -0700[diff] [blame]25CONFIG_ARCH_EARLY_INIT_R=y
Simon Glass7a99a872017-01-23 13:31:20 -0700[diff] [blame]26CONFIG_BOARD_EARLY_INIT_F=y
Tom Riniba5c2b02022-05-11 16:21:06 -0400[diff] [blame]27CONFIG_SYS_MAXARGS=32
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]28CONFIG_CMD_I2C=y
Stefan Roese88aaef02016-12-09 15:43:26 +0100[diff] [blame]29CONFIG_CMD_MMC=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]30CONFIG_CMD_PCI=y
Stefan Roesed8d20182016-10-25 11:47:51 +0200[diff] [blame]31CONFIG_CMD_SPI=y
Stefan Roesed8d20182016-10-25 11:47:51 +0200[diff] [blame]32CONFIG_CMD_USB=y
Stefan Roesed8d20182016-10-25 11:47:51 +0200[diff] [blame]33# CONFIG_CMD_SETEXPR is not set
34CONFIG_CMD_TFTPPUT=y
Stefan Roesed8d20182016-10-25 11:47:51 +0200[diff] [blame]35CONFIG_CMD_CACHE=y
36CONFIG_CMD_TIME=y
Masahiro Yamada74f09b82016-12-07 22:10:25 +0900[diff] [blame]37CONFIG_CMD_MVEBU_BUBT=y
Stefan Roesed8d20182016-10-25 11:47:51 +0200[diff] [blame]38CONFIG_CMD_EXT4_WRITE=y
Patrick Delaunayc4bbbec2017-01-27 11:00:36 +0100[diff] [blame]39CONFIG_MAC_PARTITION=y
Adam Ford710966e2020-07-03 06:48:56 -0500[diff] [blame]40CONFIG_ENV_OVERWRITE=y
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]41CONFIG_ENV_IS_IN_SPI_FLASH=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]42CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Tom Rinia8a77502022-03-11 09:12:01 -0500[diff] [blame]43CONFIG_ARP_TIMEOUT=200
Tom Rini26011a32022-03-11 09:12:02 -0500[diff] [blame]44CONFIG_NET_RETRY_COUNT=50
Ken Ma1eeac422018-05-25 15:49:27 +0800[diff] [blame]45CONFIG_AHCI_MVEBU=y
Stefan Roesed8d20182016-10-25 11:47:51 +0200[diff] [blame]46CONFIG_DM_I2C=y
47CONFIG_SYS_I2C_MVTWSI=y
48CONFIG_MISC=y
Stefan Roese88aaef02016-12-09 15:43:26 +0100[diff] [blame]49CONFIG_MMC_SDHCI=y
50CONFIG_MMC_SDHCI_XENON=y
Stefan Roesed8d20182016-10-25 11:47:51 +0200[diff] [blame]51CONFIG_SPI_FLASH_MACRONIX=y
52CONFIG_SPI_FLASH_SPANSION=y
53CONFIG_SPI_FLASH_STMICRO=y
Stefan Roese23d7dc22017-03-10 11:08:44 +0100[diff] [blame]54CONFIG_PHY_MARVELL=y
Tom Rinica22e962017-08-07 22:00:34 -0400[diff] [blame]55CONFIG_PHY_GIGE=y
Tom Rini7b1474d2021-11-07 22:59:33 -0500[diff] [blame]56CONFIG_E1000=y
Stefan Roese97c3ba02017-02-20 12:25:26 +0100[diff] [blame]57CONFIG_MVPP2=y
Mark Kettenisf8463d62022-01-22 20:38:11 +0100[diff] [blame]58CONFIG_NVME_PCI=y
Stefan Roesec20e9d52016-10-27 13:36:45 +0200[diff] [blame]59CONFIG_PCI=y
Stefan Roesec20e9d52016-10-27 13:36:45 +0200[diff] [blame]60CONFIG_PCIE_DW_MVEBU=y
Simon Glassc3fba302021-07-10 21:14:23 -0600[diff] [blame]61CONFIG_PHY=y
Stefan Roesed8d20182016-10-25 11:47:51 +0200[diff] [blame]62CONFIG_MVEBU_COMPHY_SUPPORT=y
Masahiro Yamada74f09b82016-12-07 22:10:25 +0900[diff] [blame]63CONFIG_PINCTRL=y
Stefan Roeseafa4f622017-05-09 13:35:44 +0200[diff] [blame]64CONFIG_PINCTRL_ARMADA_8K=y
Stefan Roesed8d20182016-10-25 11:47:51 +0200[diff] [blame]65CONFIG_DEBUG_UART_SHIFT=2
66CONFIG_DEBUG_UART_ANNOUNCE=y
67CONFIG_SYS_NS16550=y
Tuomas Tynkkynen13b5cb82018-02-07 02:42:22 +0200[diff] [blame]68CONFIG_KIRKWOOD_SPI=y
Stefan Roesed8d20182016-10-25 11:47:51 +0200[diff] [blame]69CONFIG_USB=y
Stefan Roesed8d20182016-10-25 11:47:51 +0200[diff] [blame]70CONFIG_USB_XHCI_HCD=y
71CONFIG_USB_EHCI_HCD=y
Chris Packham547cf412017-08-28 20:50:45 +1200[diff] [blame]72CONFIG_USB_HOST_ETHER=y
Chris Packhamb110e112017-08-28 20:50:46 +1200[diff] [blame]73CONFIG_USB_ETHER_ASIX=y
74CONFIG_USB_ETHER_MCS7830=y
75CONFIG_USB_ETHER_RTL8152=y
76CONFIG_USB_ETHER_SMSC95XX=y