blob: 9f66d79988708d3b007786224964c3d55e6db600 [file] [log] [blame]
Simon Glass8e445782019-05-07 21:41:16 -06001if TARGET_CHROMEBOOK_SAMUS || TARGET_CHROMEBOOK_SAMUS_TPL
Simon Glassa0b09612016-03-16 07:44:43 -06002
3config SYS_BOARD
4 default "chromebook_samus"
5
6config SYS_VENDOR
7 default "google"
8
9config SYS_SOC
10 default "broadwell"
11
12config SYS_CONFIG_NAME
Simon Glass8e445782019-05-07 21:41:16 -060013 default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS
14 default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS_TPL
Simon Glassa0b09612016-03-16 07:44:43 -060015
16config SYS_TEXT_BASE
17 default 0xffe00000
18
19config BOARD_SPECIFIC_OPTIONS # dummy
20 def_bool y
21 select X86_RESET_VECTOR
Andy Shevchenko3e902442020-08-20 13:02:20 +030022 select USE_EARLY_BOARD_INIT
Simon Glassa0b09612016-03-16 07:44:43 -060023 select INTEL_BROADWELL
24 select HAVE_INTEL_ME
25 select BOARD_ROMSIZE_KB_8192
Bin Meng19ca4632017-07-30 06:23:26 -070026 select SPI_FLASH_WINBOND
Simon Glassa0b09612016-03-16 07:44:43 -060027
28config PCIE_ECAM_BASE
29 default 0xf0000000
30
31config EARLY_POST_CROS_EC
32 bool "Enable early post to Chrome OS EC"
33 default y
34
35config SYS_CAR_ADDR
36 hex
37 default 0xff7c0000
38
39config SYS_CAR_SIZE
40 hex
41 default 0x40000
42
43endif
Simon Glass8e445782019-05-07 21:41:16 -060044
45if TARGET_CHROMEBOOK_SAMUS_TPL
46
47config BOARD_SPECIFIC_OPTIONS_TPL # dummy
48 def_bool y
49 select SPL
50 select TPL
51
52endif